HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 774

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.1
EDMR is a 32-bit readable/writable register that specifies E-DMAC resetting and transmit/receive
descriptor length. This register is to be set before the TR bit in EDTRR or the RR bit in EDRRR is
set to 1. If a software reset is executed with this register during data transmission, abnormal data
may be transmitted on the line. Execute a software reset with this register before specifying
transmit/receive descriptor length and modifying the settings of TDLAR, RDLAR, and so forth,
the setting of ECMR (EtherC mode register), and the settings of registers related to E-DMAC and
EtherC operation. The time required for completion of EtherC and E-DMAC initialization from a
software reset with this register is 64 cycles of the internal bus clock Bφ. Therefore, registers of
the EtherC and E-DMAC should be accessed after 64 cycles of the internal bus clock Bφ has
elapsed.
Rev. 1.00 Dec. 27, 2005 Page 730 of 932
REJ09B0269-0100
Bit
31 to 6
5
4
3 to 1
E-DMAC Mode Register (EDMR)
Bit Name
DL1
DL0
Initial
Value
All 0
0
0
All 0
R/W
R
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Descriptor Length
These bits specify the descriptor length. (See section
19.3.1, Descriptors and Descriptor List.)
00: 16 bytes
01: 32 bytes
10: 64 bytes
11: Reserved (setting prohibited)
Reserved
These bits are always read as 0. The write value
should always be 0.

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