HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 575

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

This LSI has a two-channel serial communication interface with on-chip FIFO buffers (Serial
Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous and clock
synchronous serial communication.
The SCIF provides a 16-stage FIFO register for both transmission and reception, enabling fast,
efficient, and continuous communication.
16.1
The SCIF features are listed below.
• Asynchronous mode
• Clock synchronous mode
• Full-duplex communication capability
• On-chip baud rate generator allows any bit rate to be selected.
SCIS3C3A_000020020900
level, a break is detected.
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be carried
out with standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
There is a choice of 8 serial data communication formats.
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even/odd/none
Receive error detection: Parity, framing, and overrun errors
Break detection: If a framing error is following by at least one frame at the space “0” (low)
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other chips that have a synchronous communication function.
Data length: 8 bits
Receive error detection: Overrun error
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and
continuous serial data transmission and reception.
Section 16 Serial Communication Interface with FIFO
Features
(SCIF)
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Dec. 27, 2005 Page 531 of 932
REJ09B0269-0100