HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 29

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figures
Section 1 Overview
Figure 1.1 Block Diagram .............................................................................................................. 7
Figure 1.2 Pin Assignment (HQFP2828-256(FP-256G/GV)) ........................................................ 8
Figure 1.3 Pin Assignment (P-LFBGA1717-256(BP-256H/HV)).................................................. 9
Section 2 CPU
Figure 2.1 Processing State Transitions........................................................................................ 28
Figure 2.2 Logical Address to External Memory Space Mapping................................................ 31
Figure 2.3 Register Configuration in Each Processing Mode....................................................... 34
Figure 2.4 General Registers ........................................................................................................ 36
Figure 2.5 System Registers and Program Counter ...................................................................... 37
Figure 2.6 Control Register Configuration ................................................................................... 41
Figure 2.7 Data Format on Memory (Big Endian Mode) ............................................................. 43
Figure 2.8 Data Format on Memory (Little Endian Mode) .......................................................... 43
Section 3 DSP Operating Unit
Figure 3.1 DSP Instruction Format............................................................................................... 72
Figure 3.2 CPU Registers in DSP Mode....................................................................................... 74
Figure 3.3 DSP Register Configuration ........................................................................................ 77
Figure 3.4 DSP Registers and Bus Connections ........................................................................... 94
Figure 3.5 General Registers (DSP Mode) ................................................................................... 97
Figure 3.6 Sample Parallel Instruction Program......................................................................... 113
Figure 3.7 Examples of Conditional Operations and Data Transfer Instructions ....................... 115
Figure 3.8 Data Formats ............................................................................................................. 117
Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow........................................................... 118
Figure 3.10 Operation Sequence Example.................................................................................. 120
Figure 3.11 DC Bit Generation Examples in Carry or Borrow Mode ........................................ 121
Figure 3.12 DC Bit Generation Examples in Negative Value Mode .......................................... 121
Figure 3.13 DC Bit Generation Examples in Overflow Mode.................................................... 122
Figure 3.14 ALU Integer Arithmetic Operation Flow ................................................................ 123
Figure 3.15 ALU Logical Operation Flow ................................................................................. 125
Figure 3.16 Fixed-Point Multiply Operation Flow ..................................................................... 127
Figure 3.17 Arithmetic Shift Operation Flow............................................................................. 129
Figure 3.18 Logical Shift Operation Flow.................................................................................. 131
Figure 3.19 PDMSB Operation Flow ......................................................................................... 133
Figure 3.20 Rounding Operation Flow ....................................................................................... 136
Figure 3.21 Definition of Rounding Operation........................................................................... 136
Figure 3.22 Local Data Move Instruction Flow.......................................................................... 138
Rev. 1.00 Dec. 27, 2005 Page xxvii of xlii