HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 973

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Numerics
16-bit/32-bit displacement ........................ 45
A
Absolute addresses ................................... 45
Acceptance priority and test priority ...... 162
Address space identifier (ASID)............. 189
Address transition ................................... 188
Auto-refreshing....................................... 429
Auto-request mode ................................. 477
B
Baud rate generator (BRG)..................... 613
Big endian mode....................................... 42
C
Control by slot position .......................... 620
Control registers ....................................... 32
D
Delayed branching .................................... 44
Double data transfer instructions .............. 94
DSP registers .................................... 77, 106
E
Exception handling state........................... 27
Exception request of instruction
synchronous type and instruction
asynchronous type .................................. 161
Extension of status register (SR) .............. 74
External request mode .................... 477, 487
Index
G
General registers ....................................... 32
Global base register (GBR)....................... 40
I
Instruction length ...................................... 44
IPG settings............................................. 723
L
Literal constant.......................................... 45
Little endian mode .................................... 43
Load/sStore architecture ........................... 44
Low-power consumption state .................. 27
M
Magic packet........................................... 722
MII registers.................................... 719, 720
Modulo register (MOD) ............................ 75
Multiplexed pins ..................................... 779
Multiply and accumulate registers ............ 36
O
On-chip peripheral module request......... 478
P
P0/U0 area................................................. 29
P1 area....................................................... 29
P2 area....................................................... 29
P3 area....................................................... 29
P4 area....................................................... 29
Physical address space ............................ 188
Procedure register ..................................... 36
Rev. 1.00 Dec. 27, 2005 Page 929 of 932
REJ09B0269-0100