HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 123
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
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10 000
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To control the repeat loop, the DSP extended control registers, such as the RE register and RS
register and the RC[11:0] and RF[1:0] bits of the SR register, are used. These registers can be
specified by the LDRE, LDRS, and SETRC instructions.
• Repeat end register (RE)
• Repeat start register (RS)
• Repeat counter (RC[11:0] bits of the SR)
• Repeat flags (RF[1:0] bits of the SR)
The CPU always executes instructions by comparing the RE register to program counter values.
Because the PC stores (the current instruction address +4), if the RE matches the PC during repeat
instruction detection execution, a repeat detection instruction can be detected. If a repeat detection
instruction is executed without branching and if RC[11:0] > 0, then repeat control is performed. If
RC[11:0] ≥ 2 when the repeat end instruction is completed, the RC[11:0] is decremented by 1 and
then control is passed to the address specified by the RS register.
Examples 2 to 4 show program examples of the repeat loop consisting of three instructions, two
instructions, and one instruction, respectively. In these examples, an instruction immediately prior
to the repeat start instruction is regarded as a repeat detection instruction. The RS register specifies
the specific value that indicates the number of repeat instructions.
The RE register is specified by the LDRE instruction. The RE register specifies (repeat
detection instruction address +4). In a repeat loop consisting of 4 or more instructions, an
instruction three instructions prior to the repeat end instruction is regarded as the repeat
detection instruction. A repeat loop consisting of three or less instructions is described later.
The RS register is specified by the LDRS instruction. In a repeat loop consisting of 4 or more
instructions, the RS register specifies the repeat start instruction address. In a repeat loop
consisting of three or less instructions, a specific address is specified in the RS. This is
described later.
The repeat counter is specifies the number of repetitions by the SETRC instruction. During
repeat loop execution, the RC holds the remaining number of repetitions.
The repeat flags are automatically specified according to the RS and RE register values during
SETRC instruction execution. The repeat flags store information on the number of instructions
included in the repeat loop. Normally, the user cannot modify the repeat flag values.
Rev. 1.00 Dec. 27, 2005 Page 79 of 1044
Section 3 DSP Operating Unit
REJ09B0269-0100
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