HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 473

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 Bus State Controller (BSC)
1. Auto-refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS[2:0]
in RTCSR, and the value set by in RTCOR. The value of bits CKS[2:0] in RTCOR should be
set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make
the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the
CKS[2:0] and RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts
counting up from the value at that time. The RTCNT value is constantly compared with the
RTCOR value, and if the two values are the same, a refresh request is generated and an auto-
refresh is performed for the number of times specified by the RRC[2:0]. At the same time,
RTCNT is cleared to 0 and the count-up is restarted. Figure 12.25 shows the auto-refresh cycle
timing.
After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the
banks to precharged state from active state when some bank is being precharged. Then REF
command is issued in the Trr cycle after inserting idle cycles of which number is specified by
the TRP[1:0]bits in CSnWCR. A new command is not issued for the duration of the number of
cycles specified by the TRC[1:0] bits in CSnWCR after the Trr cycle. The TRC[1:0] bits must
be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). A NOP cycle is
inserted between the Tp cycle and Trr cycle when the setting value of the TRP[1:0] bits in
CSnWCR is longer than or equal to 1 cycle.
Rev. 1.00 Dec. 27, 2005 Page 429 of 932
REJ09B0269-0100