HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 33

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 13.9 DMA Transfer Example in Cycle-Steal Mode
Figure 13.10 DMA Transfer Example in Burst Mode
Figure 13.11 Bus State when Multiple Channels are Operating ................................................. 489
Figure 13.12 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 490
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 490
Figure 13.14 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 491
Figure 13.15 Example of DREQ Input Detection in Burst Mode Level Detection .................... 491
Figure 13.16 Example of DMA Transfer End Timing (Cycle Steal Level Detection) ............... 491
Figure 13.17 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle = 1,
Section 14 Timer Unit (TMU)
Figure 14.1 TMU Block Diagram............................................................................................... 496
Figure 14.2 Setting Count Operation .......................................................................................... 501
Figure 14.3 Auto-Reload Count Operation................................................................................. 501
Figure 14.4 Count Timing when Internal Clock Is Operating .................................................... 502
Figure 14.5 UNF Set Timing ...................................................................................................... 503
Figure 14.6 Status Flag Clear Timing......................................................................................... 503
Section 15 Realtime Clock (RTC)
Figure 15.1 RTC Block Diagram................................................................................................ 506
Figure 15.2 Setting Time ............................................................................................................ 525
Figure 15.3 Reading Time .......................................................................................................... 526
Figure 15.4 Using Alarm Function ............................................................................................. 527
Figure 15.5 Example of Crystal Oscillator Circuit Connection .................................................. 528
Figure 15.6 Using Periodic Interrupt Function ........................................................................... 529
Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.1 Block Diagram of SCIF........................................................................................... 533
Figure 16.2 Data Format in Asynchronous Communication (Example of 8-Bit Data with
Figure 16.3 Sample the SCIF Initialization Flowchart ............................................................... 564
Figure 16.4 Sample Serial Transmission Flowchart ................................................................... 565
Figure 16.5 Example of Transmit Operation (Example of 8-Bit Data with Parity and
Figure 16.6 Sample Serial Reception Flowchart (1)................................................................... 568
Figure 16.7 Sample Serial Reception Flowchart (2)................................................................... 569
Figure 16.8 Example of SCIF Receive Operation (Example of 8-Bit Data with Parity and
Figure 16.9 CTS Control Operation ........................................................................................... 571
(Dual Address, DREQ Low Level Detection)......................................................... 487
Parity and 2 Stop Bits) ............................................................................................ 561
1 Stop Bit) ............................................................................................................... 567
1 Stop Bit) ............................................................................................................... 571
(Dual Address, DREQ Low Level Detection)....................................................... 487
Longword Access to 16-bit Device)...................................................................... 492
Rev. 1.00 Dec. 27, 2005 Page xxxi of xlii