HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 847

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.4.2
Table 22.4 Reset Configuration
Notes: 1. Performs normal mode and ASE mode settings
22.4.3
The timing of data output from the TDO is switched by the command type set in the SDIR. The
timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ,
SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard.
When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are
set, TDO is output at the TCK rising edge earlier than the JTAG standard by a half cycle.
ASEMD0*
H
L
2. In ASE mode, reset hold is enabled by driving the RESETP and TRST pins low for a
3. ASE mode is classified into two modes; ASE break mode to execute the firmware
4. Make sure the TRST pin is low when the power is turned on.
Reset Configuration
TDO Output Timing
1
ASEMD0 = H, normal mode
ASEMD0 = L, ASE mode
•
•
constant cycle. In this state, the CPU does not activate, even if RESETP is driven high.
When TRST is driven high, H-UDI operation is enabled, but the CPU does not activate.
The reset hold state is canceled by the following conditions:
program of an emulator and ASE user mode to execute the user program.
Another RESETP assertion (power-on reset)
TRST reassertion
RESETP
L
H
L
H
TRST
L
H
L
H
L
H
L
H
Chip State
Normal reset and H-UDI reset*
Normal reset*
H-UDI reset only
Normal operation
Reset hold*
In ASE user mode*
In ASE break mode*
H-UDI reset only
Normal operation
Section 22 User Debugging Interface (H-UDI)
Rev. 1.00 Dec. 27, 2005 Page 803 of 932
2
4
3
: Normal reset
3
: RESETP assertion is
masked
REJ09B0269-0100
4