HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 284

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Interrupt Controller (INTC)
The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral
module interrupt handling.
8.3.5
There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. The
priority of each interrupt source is set within priority levels 0 to 16; level 16 is the highest and
level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt
request is ignored.
Tables 8.2 and 8.3 list the codes for the interrupt event registers (INTEVT and INTEVT2) and the
order of interrupt priority.
Each interrupt source is assigned a unique code by INTEVT or INTEVT2. The start address of the
interrupt service routine is common for each interrupt source. This is why, for instance, the value
of INTEVT or INTEVT2 is used as an offset at the start of the interrupt service routine and
branched to in order to identify the interrupt source.
IRQ interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15
for each module by setting interrupt priority registers A to I (IPRA to IPRI). A reset assigns
priority level 0 to IRQ and on-chip peripheral module interrupts.
If the same priority level is assigned to two or more interrupt sources and interrupts from those
sources occur simultaneously, their priority order is the default priority order indicated at the right
in tables 8.2 and 8.3.
Table 8.2
Rev. 1.00 Dec. 27, 2005 Page 240 of 932
REJ09B0269-0100
Interrupt Source
NMI
H-UDI
IRQ
Interrupt Exception Handling and Priority
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
Interrupt Exception Handling Sources and Priority (IRQ Mode)
Interrupt Code*
H′1C0*
H′5E0*
H′600*
H′620*
H′640*
H′660*
H′680*
H′6A0*
3
3
3
3
3
2
3
2
1
Interrupt
Priority
(Initial Value)
16
15
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
IPR
(Bit Numbers)


IPRC (3 to 0)
IPRC (7 to 4)
IPRC (11 to 8)
IPRC (15 to 12) 
IPRD (3 to 0)
IPRD (7 to 4)
Priority
within IPR
Setting Unit







Default
Priority
High
Low