HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 793

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.2.13 E-DMAC Operation Control Register (EDOCR)
EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC
operation.
Bit
31 to 4
3
2
1 to 0
Bit Name

FEC
AEC

Initial
Value
All 0
0
0
All 0
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
FIFO Error Control
Specifies E-DMAC operation when transmit FIFO
underflow or receive FIFO overflow occurs.
0: E-DMAC operation continues when underflow or
1: E-DMAC operation halts when underflow or
Address Error Control
Indicates detection of an illegal memory address in
an attempted E-DMAC transfer.
0: Illegal memory address not detected (normal
1: Indicates that E-DMAC operation is halted because
Reserved
These bits are always read as 0. The write value
should always be 0.
overflow occurs
overflow occurs
operation)
an illegal memory address is detected. When 0 is
written to this bit, the E-DMAC resumes operation
Rev. 1.00 Dec. 27, 2005 Page 749 of 932
REJ09B0269-0100