HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 23

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

16.4 Operation ........................................................................................................................... 559
16.5 SCIF Interrupt Sources and DMAC................................................................................... 582
16.6 Usage Notes ....................................................................................................................... 583
Section 17 Serial I/O with FIFO (SIOF)............................................................587
17.1 Features.............................................................................................................................. 587
17.2 Input/Output Pins ............................................................................................................... 589
17.3 Register Descriptions ......................................................................................................... 590
17.4 Operation ........................................................................................................................... 613
16.3.7 Serial Status Register (SCFSR) ............................................................................ 545
16.3.8 Bit Rate Register (SCBRR) .................................................................................. 553
16.3.9 FIFO Control Register (SCFCR) .......................................................................... 554
16.3.10 FIFO Data Count Register (SCFDR) .................................................................... 556
16.3.11 Line Status Register (SCLSR) .............................................................................. 558
16.4.1 Overview............................................................................................................... 559
16.4.2 Serial Operation in Asynchronous Mode.............................................................. 561
16.4.3 Serial Operation in Clock Synchronous Mode...................................................... 572
17.1.1 Block Diagram...................................................................................................... 588
17.3.1 SIOF Mode Register (SIMDR) ............................................................................. 591
17.3.2 Serial Clock Select Register (SISCR)................................................................... 593
17.3.3 Serial Transmit Data Assign Register (SITDAR) ................................................. 594
17.3.4 Serial Receive Data Assign Register (SIRDAR) .................................................. 595
17.3.5 Serial Control Data Assign Register (SICDAR) ................................................... 596
17.3.6 SIOF Control Register (SICTR) ........................................................................... 598
17.3.7 SIOF FIFO Control Register (SIFCTR)................................................................ 601
17.3.8 SIOF Status Register (SISTR) .............................................................................. 603
17.3.9 SIOF Interrupt Enable Register (SIIER) ............................................................... 607
17.3.10 Serial Transmit Data Register (SITDR)................................................................ 609
17.3.11 Serial Receive Data Register (SIRDR) ................................................................. 610
17.3.12 Serial Transmit Control Data Register (SITCR) ................................................... 611
17.3.13 Serial Receive Control Data Register (SIRCR) .................................................... 612
17.4.1 Serial Clocks ......................................................................................................... 613
17.4.2 Serial Timing ........................................................................................................ 614
17.4.3 Transfer Data Format............................................................................................ 616
17.4.4 Register Allocation of Transfer Data .................................................................... 617
17.4.5 Control Data Interface .......................................................................................... 620
17.4.6 FIFO...................................................................................................................... 621
17.4.7 Transmission and Reception Procedures .............................................................. 623
17.4.8 Interrupts............................................................................................................... 628
17.4.9 Transmission and Reception Timing .................................................................... 630
Rev. 1.00 Dec. 27, 2005 Page xxi of xlii