HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 129

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Restrictions on Repeat Loop Control
1. Repeat control instruction assignment
2. Illegal instruction one or more instructions following the repeat detection instruction
Note: This restriction applies to all instructions for a repeat loop consisting of one to three
3. Instructions prohibited during repeat loop (In a repeat loop consisting of four or more
Note: Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control
The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In
addition, note that at least one instruction is required between the SETRC instruction and a
repeat start instruction.
If one of the following instructions is executed between an instruction following a repeat
detection instruction to a repeat end instruction, an illegal instruction exception occurs.
 Branch instructions
 Repeat control instructions
 Load instructions for SR, RS, and RE registers
instructions)
The following instructions must not be placed between the repeat start instruction and repeat
detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the
correct operation cannot be guaranteed.
 Repeat control instructions
 Load instructions for SR, RS, and RE registers
BRA, BSR, BT, BF, BT/F, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
instructions and to three instructions including a repeat end instruction for a repeat loop
consisting of four or more instructions.
instructions, and the external loop by other instructions such as DT or BF/S.
Rev. 1.00 Dec. 27, 2005 Page 85 of 1044
Section 3 DSP Operating Unit
REJ09B0269-0100