HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 806

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(a)
The user sets the descriptor valid/invalid bit and sets whether the descriptor represents the end of
the descriptor list in RD0 before the RR bit in EDRRR is set to 1 and the start of a read by the E-
DMAC. After completion of receive DMA transfer of an Ethernet frame by the E-DMAC, the E-
DMAC disables the descriptor valid/invalid bit and writes status information. This operation is
referred to as write-back.
When using RD0, the user should write desired values to bits 31 and 30 according to the
descriptor configuration. Write 0 to bits 29 to 0.
Rev. 1.00 Dec. 27, 2005 Page 762 of 932
REJ09B0269-0100
Bit
31
Receive Descriptor 0 (RD0)
Bit Name
RACT
Initial
Value
0
R/W
R/W
Description
Receive Descriptor Valid/Invalid
Indicates whether the corresponding descriptor is
valid or invalid. To make this bit valid, prepare a
receive buffer (user-specified receive data storage
destination) beforehand, then write 1 to this bit. The
E-DMAC clears this bit to 0 upon completion of data
transfer.
0: Indicates that the receive descriptor is invalid
1: Indicates that the receive descriptor is valid
Indicates the initial setting state, the state after 0 is
written, or (in case the user writes 1 to this bit) that
this bit is cleared to 0 because of completion of the
processing of the E-DMAC data transfer.
If this state is recognized when the E-DMAC reads
a descriptor, the E-DMAC clears the RR bit in
EDRRR to 0, and halts transfer operation related
to reception by the E-DMAC.
Indicates that data is not transferred yet after the
user writes 1 to this bit, or that data is being
transferred.
When there is a descriptor row (descriptor list)
consisting of multiple continuous descriptors, the
E-DMAC can continue operation when this bit of
the next descriptor is valid.