HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 692

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 18 Ethernet Controller (EtherC)
18.3.3
ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can
be notified to the CPU by interrupts. When 1 is written to the BRCRX, PSRTO, LCHNG, MPD,
and ICD, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that
generate interrupt, the interrupt can be enabled or disabled according to the corresponding bit in
ECSIPR.
The interrupts generated due to this status register are indicated in each ECI bit in EESR of the E-
DMAC0 derived from port0 and the E-DMAC1 derived from port1.
Rev. 1.00 Dec. 27, 2005 Page 648 of 932
REJ09B0269-0100
Bit
31 to 3 
2
1
Bit Name
LCHNG
MPD
EtherC Status Register (ECSR)
Initial
Value
All 0
0
0
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Link Signal Change
Indicates that the LNKSTA signal input from the PHY-
LSI has changed from high to low or low to high.
However, signal changes may be detected at the timing
at which the LNKSTA function was selected using
PACR of PFC.
To check the current Link state, refer to the LMON bit in
the PHY status register (PSR).
0: Change in the LNKSTA signal has not been detected
1: Change in the LNKSTA signal has been detected
Magic Packet Detection
Indicates that a Magic Packet has been detected on the
line.
0: Magic Packet has not been detected
1: Magic Packet has been detected
(high to low or low to high)

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