HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 135
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 3.8
By executing the LDRC instruction, the CPU performs the extended repeat control function. To
indicate that the CPU is being in extended repeat control, bit 0 of the RE register is set to 1 by
executing the LDRC instruction. To change the RE register value by a process such as an
exception handling, bit 0 of the RE register must be saved and restored correctly. By saving and
restoring the RC[11:0] bits, DSP bit, and RF[1:0] bits of the SR register, RE register, and RS
register correctly, a control is returned to the extended repeat function correctly after processing
such as exception handling.
Restrictions on Extended Repeat Loop Control
1. Extended repeat control instruction assignment
2. Illegal instruction one or more instructions following the repeat detection instruction
Instruction
LDRS @(disp,PC)
LDRE @(disp,PC)
LDRC #imm
LDRC Rm
The LDRC instruction must be executed after executing the LDRS and LDRE instructions. In
addition, note that at least one instruction is required between the LDRC instruction and a
repeat start instruction.
If one of the following instructions is executed as a repeat end instruction, an illegal instruction
exception occurs.
Branch instructions
Extended Repeat Control Instructions
Operation
Calculates (disp x 2 + PC) and stores the result to
the RS register
Calculates (disp x 2 + PC) and stores the result to
the RE register
Sets 8-bit immediate data imm to the RC[11:0] bits
of the SR register and sets the information related
to the number of repetitions to the RF[1:0] bits of
the SR.
RC[11:0] can be specified as 0 to 255.
During extended repeat control, bit 0 of the RE
register is set to 1.
Sets the[11:0] bits of the Rm register to the
RC[11:0] bits of the SR register and sets the
information related to the number of repetitions to
the RF[1:0] bits of the SR. RC[11:0] can be
specified as 0 to 4095.
During extended repeat control, bit 0 of the RE
register is set to 1.
Rev. 1.00 Dec. 27, 2005 Page 91 of 1044
Section 3 DSP Operating Unit
Number of Execution
States
1
1
1
1
REJ09B0269-0100
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