HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 333

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Register specifications
• Register specifications
On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B,
no user break occurs since instruction fetch is performed for an even address.
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequential mode
<Channel A>
Address:
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
Since instruction fetch is not a write cycle on channel A, a sequential condition does not
match. Therefore, no user break occurs.
BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000,
BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300001, BETR = H'0005
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
The ASID check is not included.
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
The number of execution-times break enable (5 times)
The ASID check is not included.
On channel A, a user break occurs before an instruction of address H'00000500 is executed.
On channel B, a user break occurs after the instruction of address H'00001000 are executed
four times and before the fifth time.
H'00037226, Address mask: H'00000000, ASID = H'80
H'0003722E, Address mask: H'00000000, ASID = H'70
H'00000000, Data mask: H'00000000
H'00000500, Address mask: H'00000000
H'00001000, Address mask: H'00000000
H'00000000, Data mask: H'00000000
Rev. 1.00 Dec. 27, 2005 Page 289 of 932
Section 9 User Break Controller
REJ09B0269-0100