HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 271
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Cache
address and LRU bits remain unchanged. When there is no way that receives a hit, nothing is
written and there is no operation. This function is used to invalidate a specific entry in the cache.
When the U bit of the entry that has received a hit is 1 at this point, writing back should be
performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that
entry.
6.4.2
Data Array
The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit
address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.
The address field specifies information for selecting the entry to be accessed; the data field
specifies the longword data to be written to the data array.
In the address field, specify the entry address for selecting the entry, L for indicating the longword
position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array
access. As for L, 00 indicates longword 0, 01 indicates longword 1, 10 indicates longword 2, and
11 indicates longword 3. As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2,
and 11 indicates way 3.
Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be
set to 00.
Figures 6.4 and 6.5 show the address and data formats.
The following two operations on the data array are available. The information in the address array
is not affected by these operations.
Data-Array Read: Read the data specified by L of the address filed, from the entry that
corresponds to the entry address and the way that is specified by the address filed.
Data-Array Write: Write the longword data specified by the data filed, to the position specified
by L of the address field, in the entry that corresponds to the entry address and the way specified
by the address field.
Rev. 1.00 Dec. 27, 2005 Page 227 of 932
REJ09B0269-0100
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