HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 143

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.4.2
Table 3.10 shows the relationship between the double data transfer instructions and single data
transfer instructions.
Table 3.10 Overview of Data Transfer Instructions
Addressing Mode for Double Data Transfer Instructions: The double data transfer instructions
supports the following three addressing modes.
• Non-update address register addressing
• Increment address register addressing
• Addition index register addressing
Address register
Index register
Addressing
Addressing
Modulo addressing
Data bus
Data length
Bus conflict
Memory
Source register
Destination register
The Ax and Ay registers are address pointers. They are not updated.
The Ax and Ay registers are address pointers. After a data transfer, they are each incremented
by 2 (post- increment).
The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy
register is added to each (post-increment). The double data transfer instructions do not supports
DSP Data Addressing
Double Data Transfer Instructions Single Data Transfer Instructions
MOVX.W
MOVY.W
Ax: R4, R5,
Ay: R6, R7
Ix: R8, Iy: R9
Nop/Inc (+2)/index addition:
post-increment
—
Possible
XDB, YDB
16 bits (word)
No
X/Y data memory
Dx, Dy: A0, A1
Dx: X0/X1
Dy: Y0/Y1
Rev. 1.00 Dec. 27, 2005 Page 99 of 1044
MOVS.W
MOVS.L
As: R2, R3, R4, R5
Is: R8
Nop/Inc (+2, +4)/index addition:
post-increment
Dec (–2, –4): pre-decrement
Not possible
LDB
16/32 bits (word/longword)
Yes
Entire memory space
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Section 3 DSP Operating Unit
REJ09B0269-0100