HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 628

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive
operation continues.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous
mode, the SCIF operates on a base clock with a frequency of 16 times the transfer rate.
In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is
shown in figure 16.19.
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
Rev. 1.00 Dec. 27, 2005 Page 584 of 932
REJ09B0269-0100
Base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = 0.5 –
M:
N:
D:
L:
F:
Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
2N
1
Start bit
8 clocks
– (L – 0.5)F –
16 clocks
–7.5 clocks
D – 0.5
N
(1 + F) × 100%
+7.5 clocks
D0
..................... (1)
D1