HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 399

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• CS4WCR
Bit
31 to
21
20
19
18
17
16
15 to
13
Bit Name

BAS

WW2
WW1
WW0

Initial
Value
All 0
0
0
0
0
0
All 0
R/W
R
R/W
R
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
1: Asserts the WEn (BEn) signal during the read/write
Reserved
This bit is always read as 0. The write value should always
be 0.
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for write
access.
000: The same cycles as WR3 to WR0 setting (read access
wait)
001: 0 cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
and asserts the RD/WR signal during the write access
cycle.
access cycle and asserts the RD/WR signal at the write
timing.
Rev. 1.00 Dec. 27, 2005 Page 355 of 932
Section 12 Bus State Controller (BSC)
REJ09B0269-0100