HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 26

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18.5 Connection to LSI.............................................................................................................. 725
Section 19 Ethernet Controller Direct Memory Access Controller
19.1 Features.............................................................................................................................. 727
19.2 Register Descriptions......................................................................................................... 728
19.3 Operation ........................................................................................................................... 753
19.4 Usage Notes ....................................................................................................................... 776
Rev. 1.00 Dec. 27, 2005 Page xxiv of xlii
18.4.5 MII Frame Timing ................................................................................................ 717
18.4.6 Accessing MII Registers....................................................................................... 719
18.4.7 Magic Packet Detection ........................................................................................ 722
18.4.8 Operation by IPG Setting...................................................................................... 723
18.4.9 Direction for IEEE802.1Q Qtag ........................................................................... 723
19.2.1 E-DMAC Mode Register (EDMR)....................................................................... 730
19.2.2 E-DMAC Transmit Request Register (EDTRR) .................................................. 731
19.2.3 E-DMAC Receive Request Register (EDRRR).................................................... 732
19.2.4 Transmit Descriptor List Address Register (TDLAR).......................................... 733
19.2.5 Receive Descriptor List Address Register (RDLAR) ........................................... 734
19.2.6 EtherC/E-DMAC Status Register (EESR)............................................................ 734
19.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)....................... 740
19.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 743
19.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 744
19.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 745
19.2.11 FIFO Depth Register (FDR) ................................................................................. 747
19.2.12 Receiving Method Control Register (RMCR) ...................................................... 748
19.2.13 E-DMAC Operation Control Register (EDOCR) ................................................. 749
19.2.14 Receive Buffer Write Address Register (RBWAR).............................................. 750
19.2.15 Receive Descriptor Fetch Address Register (RDFAR)......................................... 750
19.2.16 Transmit Buffer Read Address Register (TBRAR) .............................................. 750
19.2.17 Transmit Descriptor Fetch Address Register (TDFAR) ....................................... 751
19.2.18 Overflow Alert FIFO Threshold Register (FCFTR) ............................................. 751
19.2.19 Transmit Interrupt Register (TRIMD) .................................................................. 753
19.3.1 Descriptors and Descriptor List ............................................................................ 754
19.3.2 Transmission......................................................................................................... 767
19.3.3 Reception .............................................................................................................. 769
19.3.4 Transmit/Receive Processing of Multi-Buffer Frame
19.3.5 Receive FIFO Overflow Alert Signal (ARBUSY)................................................ 773
19.4.1 Using of EDTRR and EDRRR ............................................................................. 776
19.4.2 Endian Support in E-DMAC................................................................................. 777
(E-DMAC)....................................................................................... 727
(Single-Frame/ Multi-Descriptor) ........................................................................ 771