HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 330

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 User Break Controller
9.3.6
When a break occurs, the address of the instruction from where execution is to be resumed is
saved in the SPC, and the exception handling state is entered. If the L bus is specified as a break
condition, the instruction at which the break should occur can be clearly determined (except for
when data is included in the break condition). If the I bus is specified as a break condition, the
instruction at which the break should occur cannot be clearly determined.
1. When instruction fetch (before instruction execution) is specified as a break condition:
2. When instruction fetch (after instruction execution) is specified as a break condition:
3. When data access (address only) is specified as a break condition:
4. When data access (address + data) is specified as a break condition:
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The address of the instruction that matched the break condition is saved in the SPC. The
instruction that matched the condition is not executed, and the break occurs before it. However
when a delay slot instruction matches the condition, the address of the delayed branch
instruction is saved in the SPC.
The address of the instruction following the instruction that matched the break condition is
saved in the SPC. The instruction that matches the condition is executed, and the break occurs
before the next instruction is executed. However when a delayed branch instruction or delay
slot matches the condition, these instructions are executed, and the branch destination address
is saved in the SPC.
The address of the instruction immediately after the instruction that matched the break
condition is saved in the SPC. The instruction that matches the condition is executed, and the
break occurs before the next instruction is executed. However when a delay slot instruction
matches the condition, the branch destination address is saved in the SPC.
When a data value is added to the break conditions, the address of an instruction that is within
two instructions of the instruction that matched the break condition is saved in the SPC. At
which instruction the break occurs cannot be determined accurately.
When a delay slot instruction matches the condition, the branch destination address is saved in
the SPC. If the instruction following the instruction that matches the break condition is a
branch instruction, the break may occur after the branch instruction or delay slot has finished.
In this case, the branch destination address is saved in the SPC.
Value of Saved Program Counter