HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 246

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Memory Management Unit (MMU)
5.4.4
When a 1- or 4-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number
of virtual addresses are mapped onto a single physical address, the same physical address data will
be recorded in a number of cache entries, and it will not be possible to guarantee data congruity.
The reason that this problem occurs is explained below with reference to figure 5.12. The
relationship between bit n of the virtual address and cache size is shown in the following table.
To achieve high-speed operation of this LSI’s cache, an index number is created using virtual
address [n:4]. When a 1-kbyte page is used, virtual address [n:10] is subject to address translation
and when a 4-kbyte page is used, a virtual address [n:12] is subject to address translation.
Therefore, the physical address [n:10] may not be the same as the virtual address [n:10].
For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following
translation has been performed are recorded in two TLBs:
Rev. 1.00 Dec. 27, 2005 Page 202 of 932
REJ09B0269-0100
Cache Size
16 kbytes
32 kbytes
Avoiding Synonym Problems
31
0
PTEH Register
Index
31
MMUCR
31
VPN(31-17)
VPN
0
17
9
Figure 5.11 Operation of LDTLB Instruction
SV 0 0 RC 0 TF IX AT
12
VPN(11-10)
Address Array
Write
VPN
10 8
0
ASID
ASID(7-0)
Way Selection
0
0
11
12
Bit n of Virtual Address
V
Way 0 to 3
PTEL Register
PPN(28-10) PR(1-0) SZ C
31 29 28
0
0 0
PPN
10
Data Array
0 V 0 PR SZ C D SH 0
Write
D SH
0

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