HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 514

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Direct Memory Access Controller (DMAC)
Note:
Rev. 1.00 Dec. 27, 2005 Page 470 of 932
REJ09B0269-0100
Bit
7 to 3
2
1
0
*
Bit Name

AE
NMIF
DME
Only 0 can be written to clear the flag.
Initial
Value
All 0
0
0
0
R/W
R
R/(W)* Address Error Flag
R/(W)* NMI Flag
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicates that an address error occurred by the DMAC.
When this bit is set, DMA transfer is disabled even if the
DE bit in CHCR and the DME bit in DMAOR are set to 1.
This bit can only be cleared by writing 0 after reading 1.
0: No DMAC address error
1: DMAC address error
[Clear conditions]
Writing 0 after reading 1 from this bit
Indicates that an NMI interrupt occurred. When this bit is
set, DMA transfer is disabled even if the DE bit in CHCR
and the DME bit in DMAOR are set to 1. This bit can only
be cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can
be done in one transfer unit. Even if the DMAC is not in
operational, this bit is set to 1 when the NMI interrupt was
input.
0: No NMI interrupt
1: NMI interrupt occurs
[Clearing conditions]
Writing 0 after reading 1 from this bit
DMA Master Enable
Enables or disables DMA transfers on all channels. If the
DME bit and the DE bit in CHCR are set to 1, DMA
transfer is enabled. Note that transfer is enabled if the TE
bit in CHCR and the NMIF and AE bits in DMAOR are all
0. If this bit is cleared, DMA transfers in all the channels
can be terminated.
0: Disables DMA transfers on all channels
1: Enables DMA transfers on all channels