HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 340

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Power-Down Modes
Table 10.1 States of Power-Down Modes
Notes: 1. The RTC runs when the START bit in RCR2 is set to 1. For details, see section 15,
10.1.2
A reset is used at power-on or to re-execute from the initial state. This LSI supports two types of
reset: power-on reset and manual reset. In power-on reset, any processing to be currently executed
is terminated and any events not executed are canceled to execute reset processing immediately. In
manual reset, processing required to maintain external memory contents is continued. The
following shows the conditions in which power-on reset or manual reset occurs.
• Power-on reset
Rev. 1.00 Dec. 27, 2005 Page 296 of 932
REJ09B0269-0100
Mode
Sleep
mode
Software
Standby
mode
Module
standby
function
1. A low level signal is input to the RESETP pin.
2. The WDT counter overflows if the WDT starts counting while the WT/IT and RSTS bits in
3. An H-UDI reset occurs. (For details on the H-UDI reset, refer to section 22, User
WTCSR are set to 1 and cleared to 0, respectively.
Debugging Interface (H-UDI).)
2. Depends on the on-chip peripheral modules. For details, see section 1, Overview and
Reset
Transition
Conditions
Execute SLEEP
instruction with
STBY bit cleared
to 0 in STBCR
Execute SLEEP
instruction with
STBY bit set to 1
in STBCR
Set MSTP bit to 1
in STBCR,
STBCR2, and
STBCR3
Realtime Clock (RTC).
Pin Function.
CPG
EtherC
E-
DMAC
Run
Halt
Run
CPU
Halt
Halt
Run
CPU
Reg-
ister
Held
Held
Held
On-
Chip
Memory
Held
Held
Held
State
On-Chip
Periphera
l Modules
Run
Halt*
Specified
module
halts
1
Pins
Held Refreshe
Held Self-
*
2
External
Memory
d
refreshed
Refreshe
d
Canceling
Procedure
1. Interrupt
2. Reset
1. Interrupt
2. Reset
1. Clear
2. Power-
MSTP
bit to 0
on reset