HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 523

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

register. Likewise, when a transfer request is set to RXI of the SCIF0, the transfer source must be
the SCIF0's receive data register. These conditions also apply to the SCIF1, SIOF0, and SIOF1.
Depending on the on-chip peripheral module, the number of receive FIFO triggers can be set as a
transfer request. If the receive FIFO trigger condition is not satisfied, data may be remained in the
receive FIFO. Therefore, data needs to be read upon completion of the DMA transfer.
Table 13.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
13.4.3
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. The two modes (fixed mode and round-robin
mode) can be selected using bits PR0 and PR1 in DMAOR.
Fixed Mode: In this mode, the priority levels among the channels remain fixed. There are two
kinds of fixed modes as follows:
These are selected by the PR1 and the PR0 bits in DMAOR.
CHCR
RS[3:0]
1000
Channel Priority
MID
Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Fixed mode 2: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
001000
001010
010100
010101
DMARS
RID
01
10
01
10
01
10
01
10
DMA Transfer
Request
Source
SCIF0
transmitter
SCIF0
receiver
SCIF1
transmitter
SCIF1
receiver
SIOF0
transmitter
SIOF0
receiver
SIOF1
transmitter
SIOF1
receiver
DMA Transfer
Request Signal
TXI (transmit FIFO data
empty interrupt)
RXI (receive FIFO data
full interrupt)
TXI (transmit FIFO data
empty interrupt)
RXI (receive FIFO data
full interrupt)
TXI (transmit FIFO data
empty interrupt)
RXI (receive FIFO data
full interrupt)
TXI (transmit FIFO data
empty interrupt)
RXI (receive FIFO data
full interrupt)
Section 13 Direct Memory Access Controller (DMAC)
Rev. 1.00 Dec. 27, 2005 Page 479 of 932
Source
Any
SCFRDR_0
Any
SCFRDR_1
Any
SIOF0/
SIRDR_0
Any
SIOF1/
SIRDR_1
Destination
SCFTDR_0
Any
SCFTDR_1
Any
SITDR_0
Any
SITDR_1
Any
REJ09B0269-0100
Bus
Mode
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal