HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 213

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

DMA address error:
• Conditions
• Types
• Save address
• Exception code
• Remarks
4.3.3
When the address translation unit of the memory management unit (MMU) is valid, MMU
exceptions are checked after a CPU address error has been checked. Four types of MMU
exceptions are defined: TLB miss exception, TLB invalid exception, TLB protection exception,
initial page write exception. These exceptions are checked in this order.
A vector offset for a TLB miss exception is defined as H′00000400 to simplify exception source
determination. For details on MMU exception operations, refer to section 5, Memory Management
Unit (MMU).
TLB miss exception:
• Conditions
• Types
 Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +
Instruction asynchronous, processing-completion type
An address of the instruction following the instruction where an exception occurs (a delayed
branch instruction destination address if an instruction is assigned to a delay slot)
H′5C0
An exception occurs when a DMA transfer is executed while an illegal instruction address
described above is specified in the DMAC. Since the DMA transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on the DMAC, refer to section 13,
Direct Memory Access Controller (DMAC).
Comparison of TLB addresses shows no address match.
Instruction synchronous, re-execution type
3)
General Exceptions (MMU Exceptions)
Rev. 1.00 Dec. 27, 2005 Page 169 of 932
Section 4 Exception Handling
REJ09B0269-0100