HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 771

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

This LSI has an on-chip two-channel direct memory access controller (E-DMAC0/1) directly
connected to the Ethernet controller (EtherC). By using the DMAC contained in the E-DMAC, the
E-DMAC transfers transmit/receive data between the transmit/receive FIFO in the E-DMAC and a
user-specified data storage destination (buffer) by DMA transfer. At DMA transfer, information
referenced by the E-DMAC is referred to as a transmit/receive descriptor, and the user places this
descriptor in memory.
This function reduces the load on the CPU and enables efficient data transfer control to be
achieved. The E-DMAC0 and E-DMAC1 control the data transmission/reception from the MAC-0
and MAC-1 of EtherC respectively. (Hereafter the channel controlled by the E-DMAC0 is channel
0. The channel controlled by the E-DMAC1 is channel 1.)
Figure 19.1 shows the configuration of the E-DMAC, and the descriptors and transmit/receive
buffers in memory.
19.1
The E-DMAC has the following features:
• Contains two-channel independent transmit/receive DMAC
• The load on the CPU is reduced by means of a descriptor management system
• Transmit/receive frame status information is indicated in descriptors
• Achieves efficient system bus utilization through the use of DMA block transfer (16-byte
• Supports single-frame/single-descriptor operation and single-frame/multi-frame (multi-buffer)
Note: The E-DMAC cannot access peripheral modules.
EDMAS20B_000020020900
units)
operation
Section 19 Ethernet Controller Direct Memory Access
Features
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Controller (E-DMAC)
Rev. 1.00 Dec. 27, 2005 Page 727 of 932
REJ09B0269-0100