HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 118

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
3.2.3
In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three
control registers: a repeat start register (SR), repeat end register (RE), and module register are
added as control registers.
Extension of Status Register (SR): In DSP mode, the following control bits are added to the
status register (SR). These added bits are called DSP extension bits. These DSP extension bits are
valid only in DSP mode.
Rev. 1.00 Dec. 27, 2005 Page 74 of 1044
REJ09B0269-0100
Bit
31 to 28 
27 to 16 RC11 to
15 to 13 
12
31
31
31
31
0
MD RB BL
30
29
ME
Bit Name
RC0
DSP
CPU Register Sets
28 27
RC[11:0]
16 15
RS
RE
Initial
Value

All 0

0
16 15
Figure 3.2 CPU Registers in DSP Mode
0
R/W

R/W

R/W
MS
14
0
13
0 DSP DMY DMX M
Description
For details, refer to section 2, CPU.
Repeat Counter
Holds the number of repeat times in order to perform loop
control, and can be modified in privileged mode, privileged
DSP mode, or user DSP mode. At reset, this bit is initialized
to 0. This bit is not affected in the exception handling state.
For details, refer to section 2, CPU.
DSP Bit
Enables or disables the DSP extended functions. If this bit
is set to 1, the DSP extended functions are enabled. This bit
can be modified in privileged mode or privileged DSP mode.
This bit cannot be modified in user DSP mode. At reset, this
bit is initialized to 0. This bit is not affected in the exception
handling state.
12
0
0
0
11
Repeat Start register (RS)
Repeat End register (RE)
MODulo register (MOD)
10
9
Q
8
I3
7
I2
6
I1
5
I0 RF1 RF0 S
4
3
2
1
0
T
Status Register
(SR)