HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 777

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note:
19.2.4
TDLAR is a 32-bit readable/writable register that specifies the start address of the transmit
descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length
indicated by the DL bit in EDMR. This register must not be written to during transmission.
Modifications to this register should only be made while transmission is disabled by the TR bit
(= 0) in the E-DMAC transmit request register (EDTRR).
Bit
31 to 1
0
Bit
31 to 0
*
Transmit Descriptor List Address Register (TDLAR)
Bit Name

RR
Bit Name
TDLA31 to
TDLA0
If the receive function is disabled during frame reception, write-back is not performed
successfully to the receive descriptor. Following pointers to read a receive descriptor
become abnormal and the E-DMAC can not operate successfully. In this case, to make
the E-DMAC reception enabled again, execute a software reset by the SWR bit in
EDMR0 (EDMR1). To make the E-DMAC reception disabled without executing a
software reset, specify the RE bit in ECMR0 (ECMR1). Next, after the E_DMAC has
completed the reception and write-back to the receive descriptor has been confirmed,
disable the receive function of this register.
Initial
Value
All 0
Initial
Value
All 0
0
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Request
0: The receive function is disabled*
1: A receive descriptor is read, and the E-DMAC is
Description
Transmit Descriptor Start Address
The lower bits are set as follows according to the
specified descriptor length.
16-byte boundary: TDLA3 and TDLA0 = 0000
32-byte boundary: TDLA4 and TDLA0 = 00000
64-byte boundary: TDLA5 and TDLA0 = 000000
ready to receive
Rev. 1.00 Dec. 27, 2005 Page 733 of 932
REJ09B0269-0100