HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 39

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 1 Overview
Table 1.1
Table 1.2
Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Section 3 DSP Operating Unit
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Table 3.12
Table 3.13
Table 3.14
Table 3.15
Table 3.16
Table 3.17
Table 3.18
Table 3.19
Pin Assigument ....................................................................................................... 10
Pin Functions .......................................................................................................... 19
Logical Address Space............................................................................................ 30
Register Initial Values............................................................................................. 33
Addressing Modes and Effective Addresses for CPU Instructions......................... 45
CPU Instruction Formats ........................................................................................ 49
CPU Instruction Types............................................................................................ 52
Data Transfer Instructions....................................................................................... 56
Arithmetic Operation Instructions .......................................................................... 58
Logic Operation Instructions .................................................................................. 60
Shift Instructions..................................................................................................... 61
Branch Instructions ................................................................................................. 62
System Control Instructions.................................................................................... 63
Operation Code Map............................................................................................... 66
Logical Address Space............................................................................................ 73
Operation of SR Bits in Each Processing Mode ..................................................... 76
RS and RE Setting Rule.......................................................................................... 82
Repeat Control Instructions .................................................................................... 82
Repeat Control Macros ........................................................................................... 83
DSP Mode Extended System Control Instructions ................................................. 84
PC Value during Repeat Control (When RC[11:0] ≥ 2) ......................................... 87
Extended Repeat Control Instructions .................................................................... 91
Extended System Control Instructions in DSP Mode ............................................. 96
Overview of Data Transfer Instructions.................................................................. 99
Modulo Addressing Control Instructions.............................................................. 101
Double Data Transfer Instruction Formats ........................................................... 104
Single Data Transfer Instruction Formats ............................................................. 105
Destination Register in DSP Instructions.............................................................. 107
Source Register in DSP Operations ...................................................................... 108
DSR Register Bits................................................................................................. 109
DSP Operation Instruction Formats ...................................................................... 112
Correspondence between DSP Instruction Operands and Registers ..................... 112
DC Bit Update Definitions.................................................................................... 114
Tables
Rev. 1.00 Dec. 27, 2005 Page xxxvii of xlii