DS3181 Maxim Integrated Products, DS3181 Datasheet
DS3181
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DS3181 Summary of contents
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... GENERAL DESCRIPTION The DS3181, DS3182, DS3183, and DS3184 (DS318x) integrate ATM processor(s) with a DS3/E3 framer(s) and LIU(s) to map/demap ATM cells or packets into as many as four DS3/E3 physical copper lines with DS3-framed, E3-framed, or clear-channel data streams on per-port basis. APPLICATIONS Access Concentrators Multiservice Access ...
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... DS3, E3, and PLCP Framers DETAILED DESCRIPTION The DS3181 (single), DS3182 (dual), DS3183 (triple), and DS3184 (quad) PHYs perform all the functions necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3 (34.368Mbps) framed, or 52Mbps clear-channel data streams on DS3, E3, or STS-1 physical copper lines. Each line interface unit (LIU) has independent receive and transmit paths ...
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BLOCK DIAGRAMS 2 APPLICATIONS 3 FEATURE DETAILS 3 .......................................................................................................................17 LOBAL EATURES 3.2 R DS3/E3/STS-1 LIU F ECEIVE 3.3 R DS3/E3 F ECEIVE RAMER 3.4 R PLCP F ECEIVE RAMER 3 ECEIVE ELL ROCESSOR 3.6 ...
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HORT IN ESCRIPTIONS 8 ETAILED IN ESCRIPTIONS 8 UNCTIONAL IMING 8.3.1 Line IO.................................................................................................................................................. 66 8.3.2 DS3/E3 Framing and PLCP Overhead Functional Timing................................................................... 69 8.3.3 Internal (IFRAC) and External (XFRAC) ...
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ATM C /HDLC P ELL ACKET 10.7.1 General Description ........................................................................................................................... 139 10.7.2 Features ............................................................................................................................................. 139 10.7.3 Transmit Cell/Packet Processor......................................................................................................... 140 10.7.4 Receive Cell/Packet Processor.......................................................................................................... 141 10.7.5 Cell Processor.................................................................................................................................... 141 10.7.6 Packet Processor ............................................................................................................................... 146 10.7.7 FIFO ................................................................................................................................................... 148 10.7.8 ...
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Features ............................................................................................................................................. 190 10.14.3 B3ZS/HDB3 Encoder ......................................................................................................................... 190 10.14.4 Transmit Line Interface ...................................................................................................................... 191 10.14.5 Receive Line Interface ....................................................................................................................... 191 10.14.6 B3ZS/HDB3 Decoder ......................................................................................................................... 191 10.15 BERT.........................................................................................................................................193 10.15.1 General Description ........................................................................................................................... 193 10.15.2 Features ............................................................................................................................................. 193 10.15.3 Configuration and ...
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Receive G.751 E3 Register Map ....................................................................................................... 291 12.10.5 Transmit G.832 E3 Register Map ...................................................................................................... 297 12.10.6 Receive G.832 E3 Register Map ....................................................................................................... 300 12.10.7 Transmit Clear Channel ..................................................................................................................... 309 12.10.8 Receive Clear Channel ...................................................................................................................... 310 12.11 F DS3/E3 ..................................................................................................................312 ...
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Figure 1-1. LIU External Connections for a DS3/E3/STS-1 Port of a DS318x Device.............................................. 14 Figure 1-2. DS318x Functional Block Diagram ......................................................................................................... 14 Figure 2-1. Four-Port Unchannelized ATM over DS3/E3/CC52 Line Card ............................................................... 15 Figure 2-2. Four-Port Unchannelized HDLC over DS3/E3/CC52 ...
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Figure 8-39. POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing........................................... 86 Figure 8-40. 16-Bit Mode Write.................................................................................................................................. 87 Figure 8-41. 16-Bit Mode Read ................................................................................................................................. 87 Figure 8-42. 8-Bit Mode Write.................................................................................................................................... 88 Figure 8-43. 8-Bit Mode Read ................................................................................................................................... 88 Figure 8-44. ...
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... Figure 14-2. DS3183 Pin Assignments—400-Lead TE-PBGA................................................................................ 378 Figure 14-3. DS3182 Pin Assignments—400-Lead TE-PBGA................................................................................ 378 Figure 14-4. DS3181 Pin Assignments—400-Lead TE-PBGA................................................................................ 379 Figure 18-1. Clock Period and Duty Cycle Definitions............................................................................................. 384 Figure 18-2. Rise Time, Fall Time, and Jitter Definitions......................................................................................... 384 Figure 18-3 ...
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Table 4-1. Standards Compliance ............................................................................................................................. 23 Table 6-1. DS3/E3 ATM/Packet Mode Configuration Registers................................................................................ 26 Table 6-2. DS3/E3 ATM/Packet—OHM Mode Configuration Registers.................................................................... 27 Table 6-3. DS3/E3 Internal Fractional (IFRAC) ATM/Packet Mode Configuration Registers ................................... 28 Table 6-4. DS3/E3 External Fractional (XFRAC) ...
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Table 10-39. Repetitive Pattern Generation ............................................................................................................ 194 Table 10-40. Transformer Characteristics ............................................................................................................... 199 Table 10-41. Recommended Transformers............................................................................................................. 200 Table 11-1. Global and Test Register Address Map ............................................................................................... 203 Table 11-2. Per-Port Register Address Map ........................................................................................................... 203 Table 12-1. Global Register ...
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Table 17-1. Recommended DC Operating Conditions ............................................................................................ 382 Table 17-2. DC Electrical Characteristics................................................................................................................ 382 Table 17-3. Output Pin Drive ................................................................................................................................... 383 Table 18-1. Fractional Port Timing .......................................................................................................................... 386 Table 18-2. Line Interface Timing ............................................................................................................................ 386 Table 18-3. Miscellaneous Pin Timing..................................................................................................................... ...
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BLOCK DIAGRAMS Figure 1-1 shows the external components required at each LIU interface for proper operation. the functional block diagram of one channel ATM/Packet PHY. Figure 1-1. LIU External Connections for a DS3/E3/STS-1 Port of a DS318x Device Transmit ...
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APPLICATIONS • Access Concentrators • Multiservice Access Platforms • ATM and Frame Relay Equipment • Routers and Switches • SONET/SDH ADM • SONET/SDH Muxes • PBXs • Digital Cross Connect • PDH Multiplexer/Demultiplexer • Test Equipment • Integrated Access ...
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Figure 2-2. Four-Port Unchannelized HDLC over DS3/E3/CC52 Line Card Typical Packet Line Card DS315x #1 DS3154 #1 4- Chan 4- Chan x DS3/E3 DS3/E3 DS3/E DS3/E3 Line Line LIU LIU DS318x DS3154 #3 DS315x #3 4- Chan 4- Chan x ...
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... FEATURE DETAILS The following sections describe the features provided by the DS3181 (single), DS3182 (dual), DS3183 (triple), and DS3184 (quad) PHYs. 3.1 Global Features • System interface configurable for UTOPIA L2/UTOPIA L3 for ATM cell traffic or POS-PHY L2/POS-PHY L3 or SPI-3 for HDLC packets or mixed packet/cell traffic • ...
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Detection of RDI, AIS, DS3 idle signal, loss of signal (LOS), severely errored framing event (SEFE), change of frame alignment (COFA), receipt of B3ZS/HDB3 code words, DS3 application ID bit, DS3 M23/C-bit format mismatch, G.751 national bit, and G.832 ...
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Receive FIFO Features • Storage capacity for four cells or 256 bytes of packet data per port • Programmable port address • Programmable fill level thresholds • Underflow and overflow status indications 3.8 Receive System Interface Features • UTOPIA ...
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Transmit PLCP Formatter Features • Insertion of FAS bytes (A1, A2), path overhead identification (POI) bytes, and path overhead bytes • Generation of BIP-8 (B1), FEBE and RAI (G1) • C1 cycle/stuff counter generation referenced to GPIO4 input pin, ...
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Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode and optionally the G.751 Sn bit or the G.832 channels or PLCP F1 bytes • RX data is forced to all ones ...
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Externally controlled with DS3 or E3 payload manipulating capability • (XFRAC) Externally controlled with flexible DS3 or E3 data rate reduction capability • (IFRAC) Internally controlled with simple DS3 or E3 data rate reduction capability • Subrate algorithm ...
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STANDARDS COMPLIANCE Table 4-1. Standards Compliance SPECIFICATION ANSI T1.102-1993 Digital Hierarchy – Electrical Interfaces T1.107-1995 Digital Hierarchy – Formats Specification T1.231-1997 Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring T1.404-1994 Network-to-Customer Installation – DS3 Metallic Interface Specification ...
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SPECIFICATION Hierarchy, 1993 Transport of SDH Elements on PDH Networks – Frame and Multiplexing Structures, G.832 November, 1995 I.432 B-ISDN User-Network Interface – Physical Layer Specification, March, 1993 Error Performance Measuring Equipment Operating at the Primary Rate and Above, O.151 ...
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ACRONYMS AND GLOSSARY Definition of the terms used in this data sheet: Acronyms • ATM – Asynchronous Transfer Mode • CC52 – Clear-Channel 52 Mbps (STS-1 Clock Rate) • CLAD – Clock Rate Adapter • CLR – Clear-Channel Mode ...
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MAJOR OPERATIONAL MODES The major operational modes are determined by the FM[5:0] framer mode bits and a few other control bits. Unused features are powered down and the data paths are held in reset. The configuration registers of the ...
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DS3/E3 ATM/Packet—OHM Mode DS3/E3 ATM/Packet—OHM Mode is a normal mode of operation for the DS318x devices, which maps/demaps ATM cells or packet data into a DS3 or E3 data stream, supporting externally defined framing protocols. Major functional blocks for ...
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DS3/E3 Internal Fractional (Subrate) ATM/Packet Mode DS3/E3 Internal Fractional Mode allows subrate datastreams to be inserted into a DS3 or E3 line, with the fractional overhead internally controlled. Major functional blocks for the DS3/E3 Internal Fractional Mode are shown ...
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DS3/E3 External Fractional (Subrate) ATM/Packet Mode DS3/E3 External Fractional Mode allows subrate datastreams to be inserted into a DS3 or E3 line, with the fractional overhead externally controlled. Major functional blocks for the DS3/E3 Internal Fractional Mode are shown ...
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DS3/E3 Flexible External Fractional (Subrate) Mode Configuration Mode DS3/E3 Flexible External Fractional Mode allows subrate datastreams to be inserted into a DS3 or E3 line, with the fractional overhead and payload externally multiplexed. Major functional blocks for the DS3/E3 ...
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DS3/E3 G.751 PLCP ATM Mode DS3/E3 G.751 PLCP ATM mode is a normal mode of operation for the DS318x devices, which maps/demaps ATM cells into/from the DS3/E3 PLCP data stream. Major functional blocks for the DS3/E3 ATM/Packet mode are ...
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DS3/E3 G.751 PLCP ATM—OHM Mode DS3/E3 G.751 PLCP ATM—OHM mode is a normal mode of operation for the DS318x devices, which maps/demaps ATM cells into/from the DS3/E3 PLCP data stream, supporting externally defined framing modes. Major functional blocks for ...
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Figure 6-7. DS3/E3 G.751 PLCP ATM—OHM Mode TOHMIn TUA1 TDATn TOHMOn TLCLKn RLCLKn RDATn ROHMIn Clock Rate Adapter DS3/E3 Transmit TX PLCP Formatter TRAIL FEAC HDLC TRACE DS3/E3 Receive Framer UA1 IEEE 1149.1 GEN JTAG Test Access Port 33 Tx ...
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Clear-Channel ATM/Packet Mode The Clear-Channel ATM/Packet Mode maps/demaps ATM cells or HDLC packets into/from a serial datastream, bypassing the DS3/E3 formatter/framer. Major functional blocks for the Clear-Channel ATM/Packet Mode are shown in Figure 6-8. Mapping configuration is programmable on ...
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Clear-Channel ATM/Packet—OHM Mode The Clear-Channel ATM/Packet—OHM Mode maps/demaps ATM cells or HDLC packets into/from a serial datastream, bypassing both the DS3/E3 formatter/framer and the LIU, supporting externally defined framing modes. Major functional blocks for the Clear-Channel ATM/Packet—OHM Mode are ...
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Clear-Channel Octet Aligned ATM/Packet—OHM Mode The Clear-Channel Octet Aligned ATM/Packet—OHM Mode maps/demaps ATM cells or HDLC packets into/from a serial datastream, bypassing both the DS3/E3 formatter/framer and the LIU, supporting arbitrary framing modes. Major functional blocks for the Clear-Channel ...
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MAJOR LINE INTERFACE OPERATING MODES The line interface modes provide the following functions: 1. Enabling/disabling of RX and TX LIU. 2. Enabling/Disabling of jitter attenuator (JA). 3. Selection of the location of JA, i.e path. 4. ...
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Figure 7-1. HDB3/B3ZS/AMI LIU Mode TXPn DS3/E3 Encoder Transmit TXNn LIU DS3/E3 RXPn Receive RXNn LIU Decoder Clock Rate Adapter TAIS TUA1 B3ZS/ HDB3 FROM FRAMING LOGIC OR EXTERNAL PINS B3ZS/ TO FRAMING LOGIC HDB3 OR EXTERNAL PINS 38 n ...
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HDB3/B3ZS/AMI Non-LIU Line Interface Mode The Non-LIU Line Interface Mode disables the LIU and a digital representation of AMI is output/input on the TPOSn/TNEGn signals and the RPOSn/RNEGn signals. Selection between AMI and HDB3/B3ZS is made via the LINE.TCR ...
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UNI Line Interface Mode This mode is valid for all framing modes, providing a digital NRZ input/output on RDATn and TDATn and clocked by RLCLKn and TLCLKn. The B3ZS/HDB3 decoder/encoder block is disabled except for the BPV counter, which ...
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UNI Line Interface—OHM Mode The line interface is forced into UNI mode when the framer is in any OHM mode; therefore, the LM bits are Don’t Cares. This mode is the same as the UNI Line Interface Mode except ...
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PIN DESCRIPTIONS Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board-level ATPG patterns for isolation of interconnect failures. 8.1 Short Pin Descriptions Table 8-1. DS3184 Short Pin Descriptions n = 1,2,3,4 (port number). ...
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NAME TYPE RSOFOn / RDENn / RPOHSOFn / O RFOHENOn NAME TYPE UTOPIA L2/L3 OR POS-PHY L2/3 OR SPI-3 SYSTEM INTERFACE TSCLK I TADR[4] TADR[3] I TADR[2] TADR[1] TADR[0] TDATA[31] TDATA[30] TDATA[29] TDATA[28] TDATA[27] TDATA[26] TDATA[25] TDATA[24] TDATA[23] TDATA[22] TDATA[21] ...
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NAME TYPE TSPA Oz TEOP I TSX I TMOD[1] I TMOD[0] TERR I RSCLK I RADR[4] RADR[3] RADR[2] I RADR[1] RADR[0] RDATA[31] RDATA[30] RDATA[29] RDATA[28] RDATA[27] RDATA[26] RDATA[25] RDATA[24] RDATA[23] RDATA[22] RDATA[21] RDATA[20] RDATA[19] RDATA[18] RDATA[17] RDATA[16] Oz RDATA[15] RDATA[14] ...
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NAME TYPE REOP Oz Receive End Of Packet RVAL Oz Receive Packet Data Valid RMOD[1] Oz Receive Packet Data Modulus [1:0] RMOD[0] RERR Oz Receive Packet Error D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] IO Data [15:0] D[7] D[6] ...
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NAME TYPE MISC I/O GPIO[8] GPIO[7] GPIO[6] GPIO[5] IO GPIO[4] GPIO[3] GPIO[2] GPIO[1] TEST I HIZ I RST I JTCLK I JTMS Ipu JTDI Ipu JTDO Oz JTRST Ipu CLKA I CLKB IO CLKC IO VSS PWR VDD PWR FUNCTION ...
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NAME TYPE AVDDRn PWR Analog 3.3V for Receive LIU on Port n AVDDTn PWR Analog 3.3V for Transmit LIU on Port n AVDDJn PWR Analog 3.3V for Jitter Attenuator on Port n AVDDC PWR Analog 3.3V for CLAD NO CONNECTS ...
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Detailed Pin Descriptions Table 8-2. Detailed Pin Descriptions n = 1,2,3,4 (port number). Ipu (input with pullup), Oz (output tri-stateable) (needs an external pullup or pulldown resistor to keep from floating), Oa (Analog output), Ia (analog input), IO (bidirectional ...
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PIN TYPE Transmit Negative AMI / Line OH Mask TNEGn: When the port line is configured for B3ZS, HDB3 or AMI mode and the framer is not configured for one of the “-OHM” modes (see transmit line interface pins are ...
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PIN TYPE Receive Line Clock Input RLCLKn: This clock is typically used for the reference clock for the RPOSn / RDATn, RNEGn / RLCVn / ROHMIn signals but can also be used as the reference clock for the RSERn, RSOFOn ...
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PIN TYPE Transmit Overhead / Line OH Mask Input TOHn: When the port framer is configured for one of the DS3 or E3 framing modes, this signal will be used to over-write the DS3 or E3 framing overhead bits when ...
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PIN TYPE Receive Overhead Start Of Frame ROHSOFn: When the port framer is configured for one of the DS3 or E3 framing modes this signal is used to mark the start of a DS3 or E3 overhead sequence on the ...
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PIN TYPE PLCP framing overhead bits when TPOHENn is active. The TPOHSOFn signal marks the start of the framing bit sequence. This signal is sampled at the same time as the TPOHCLKn signal transitions high to low. This signal can ...
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PIN TYPE framing modes, the port pins are enabled and the TCLKOn pin function is not selected, this clock is used for the transmit overhead port signals TPOHn, TPOHENn and TPOHSOFn. The TPOHSOFn output signal is updated and the TPOHn ...
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PIN TYPE Transmit Payload Data Enable Output. See TPDENOn: When the port framer is enabled for the Flexible fractional mode and the port pins are enabled, this signal marks which bits on the TPDATn pin are valid payload data bits. ...
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PIN TYPE DS3: 44.736 Mbps +20ppm o E3: 34.368 Mbps +20ppm o CC52: 52 Mbps +20ppm o RPOHn: When the port framer is configured for one of the PLCP framing modes and the port pins are enabled, this signal outputs ...
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PIN TYPE Receive Framer Start Of Frame /Data Enable / PLCP Overhead Start Of Frame. See Table 10-30. RSOFOn: When the port framer is configured for External Fractional or Flexible Fractional mode and the RSOFOn pin function is enabled, or ...
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PIN TYPE In 8-bit mode, TDATA[7] is the MSB, TDATA[0] is the LSB, and TDATA[31:8] are not used and ignored. Transmit Parity TPRTY: This signal indicates the parity on the data bus when parity checking is TPRTY I enabled. This ...
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PIN TYPE TSPA goes low when the selected port is "full" port is selected. This signal is updated on the rising edge of TSCLK. In UTOPIA L3 mode this signal is low. In POS-PHY L2 mode, this signal ...
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PIN TYPE Receive Data [31:0] (tri-state) This signal is tri-state when global reset is applied. RDATA[31:0]: This 32-bit data bus is used to transfer cell/packet data to the ATM/Link layer device. This bus is updated on the rising edge of ...
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PIN TYPE In UTOPIA L2 or UTOPIA L3 modes, RPXA goes high when the polled port has more than a programmable number of ATM cells ready for transfer ("almost empty" level of the associated FIFO). RPXA goes low when the ...
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PIN TYPE Receive Packet Data Valid (tri-state) This signal is tri-state when global reset is applied. RVAL: In POS-PHY L2 or POS-PHY L3 modes, this signal is used to indicate the validity of a receive data transfer. When RVAL is ...
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... A[10:1] I A[10:1]: identifies the specific 16 bit registers, or group of 8 bit registers, being accessed. A[10] must be tied to ground for the DS3181 and DS3182 versions. Address Bus LSB / Byte Swap A[0]: This signal is connected to the lower address bit in 8-bit systems. (WIDTH= Output register bits 15:8 on D[7:0], D[15:8] not driven ...
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PIN TYPE General-Purpose IO 1 GPIO1: This signal is configured general-purpose IO pin alarm output GPIO1 IO signal for port 1. This pin is an input after reset and should have a pullup resistor on ...
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PIN TYPE JTAG Clock JTCLK I JTCLK: This clock input is typically a low frequency (less than 10 MHz) 50% duty cycle clock signal. JTAG Mode Select (with pullup) JTMS Ipu JTMS: This input signal is used to control the ...
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Pin Functional Timing 8.3.1 Line IO 8.3.1.1 B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing There is no suggested time alignment between the TXPn, TXNn and TX LINE signals and the TLCLKn clock signal. The TX DATA signal is not a ...
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Figure 8-2. TX Line IO HDB3 Functional Timing Diagram TLCLK (TX DATA) TPOS TNEG TXP BIAS V TXN (TX LINE) - 8.3.1.2 B3ZS/HDB3/AMI Mode Receive Pin Functional Timing There is no suggested time alignment between the RXPn, ...
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Figure 8-4. RX Line IO HDB3 Functional Timing Diagram RLCLK (RX DATA) RPOS RNEG RXP BIAS V RXN (RX LINE) - 8.3.1.3 UNI Mode Transmit Pin Functional Timing The TDATn pin is available when the line interface ...
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UNI Mode Receive Pin Functional Timing The RDATn pin is available when the line interface is in the UNI mode. The ROHMIn pin is available when the framer is in one of the “-OHM” modes. The RLCVn pin is ...
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Figure 8-10 shows the relationship of the E3 G.751 receive-overhead port pins. Figure 8-10. E3 G.751 Framing Receive Overhead Port Timing ROHCLK ROHSOF FAS FAS FAS ROH Figure 8-11 shows ...
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Figure 8-14 shows the relationship of the E3 G.832 transmit-overhead port pins. Figure 8-14. E3 G.832 Framing Transmit Overhead Port Timing TOHCLK TOHSOF TOHEN FA1 FA1 TOH ...
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Figure 8-18 shows the relationship of the E3 G.751 PLCP transmit-overhead port pins. Figure 8-18. E3 G.751 PLCP Transmit Overhead Port Timing TPOHCLK TPOHSOF TPOHEN TPOH ...
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Figure 8-21 shows the timing with the internal fractional transmit port pins. Figure 8-21. Internal (IFRAC) Transmit Fractional Timing TCLKI or TCLKO TGCLK TFOHENO TFOH FOH Figure 8-22 shows the timing with ...
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Figure 8-23 shows the timing with the flexible fractional transmit port pins. Figure 8-23. Transmit Flexible Fractional (FFRAC) Timing TCLKI or TCLKO TPDENI TPDENO TPDAT TSOFI TSOFO TDEN TSER FPx FPy FPz FOx FOy ...
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UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing 8.3.5.1 UTOPIA Level 2 Functional Timing Figure 8-25 shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2, the ATM device places address ‘00h’ on the address bus (which ...
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Figure 8-26 shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2, the ATM device places address ‘00h’ on the address bus (which is mapped to Port 1). PHY device '1' (Port 1) indicates to ...
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Figure 8-27. UTOPIA Level 2 Transmit Multiple Cell Transfer Polled Mode TCLK TADR TPXA M N TEN TDATA TSOX Transfer Cell To: Figure 8-28 shows a multidevice receive-interface multiple cell transfer ...
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Figure 8-29. UTOPIA Level 2 Receive Unexpected Multiple Cell Transfer RCLK RADR RPXA L M REN* RDAT P45 P46 P47 RSOX Transfer N Cell From 8.3.5.2 UTOPIA Level 3 Functional Timing Figure ...
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Figure 8-31 shows a multiport transmit-interface multiple cell transfer to different PHY devices. On clock edge 1, the ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it can accept ...
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Figure 8-32. UTOPIA Level 3 Receive Multiple Cell Transfer Direct Mode RSCLK RADR RDXA[1] RDXA[2] RDXA[3] RDXA[4] REN RDATA RSOX Transfer Cell From Figure 8-33 shows a multiport receive-interface multiple cell transfer from different PHY ports. ...
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POS-PHY Level 2 Functional Timing Figure 8-34 shows a multidevice transmit interface in byte transfer mode multiple packet transfer to different PHY ports. Prior to clock edge 1, the POS device started a packet transfer to PHY port '1'. ...
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On clock edge 14, PHY port '3' places the last byte of the packet on RDATA, and asserts REOP to indicate that this is the last transfer of the packet. On clock edge 15, PHY port '3' deasserts RVAL and ...
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Figure 8-36. POS-PHY Level 2 Transmit Multiple Packet Transfer to Different PHY Ports (polled status mode) TCLK TADR TPXA M N TSPA TEN TDAT TSOX TEOP TERR Transfer To PHY ...
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Figure 8-37. POS-PHY Level 2 Receive Multiple Packet Transfer (polled status mode) RCLK RADR RPXA M N REN RVAL RDAT RSOX REOP RERR Transfer From PHY … ...
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POS-PHY Level 3 Functional Timing Figure 8-38 shows a multiport transmit interface multiple packet transfer to different PHY ports. On clock edge 1, PHY port 'N' indicates to the POS device that it can accept a block of packet ...
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Figure 8-39. POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing RCLK REN RVAL RSX RDAT RSOX REOP RERR Transfer From PHY … P62 P63 P64 ...
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Microprocessor Interface Functional Timing Figure 8-40 and Figure 8-42 shows examples of a 16-bit databus and an 8-bit databus, respectively. In 16-bit mode, the A[0]/BSWAP signal controls whether or not to byte swap. In 8-bit mode, the A[0]/BSWAP signal ...
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Figure 8-42. 8-Bit Mode Write A[0]/BSWAP 0x2B0 A[10:1] D[7:0] 0x34 RDY Z Note: Address 0x2B0 = 0x34 0x2B1 = 012 Figure 8-43. 8-Bit Mode Read A[0]/BSWAP 0x2B0 A[10:1] D[7:0] 0x34 RDY Z Note: Address ...
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Figure 8-44. 16-Bit Mode without Byte Swap A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 0x2B2 = 0x5678 Figure 8-45. 16-Bit Mode with Byte Swap A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x3412 ...
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Figure 8-46. Clear Status Latched Register on Read A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z Figure 8-47. Clear Status Latched Register on Write A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Figure 8-48 and Figure ...
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Figure 8-49. RDY Signal Functional Timing Read A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z See also Figure 18-7 and Figure 8.3.7 JTAG Functional Timing See Section 13.5. 0x3A4 0xFFFF Z Z 18- ...
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... STEP 1: Check Device ID Code. Before any testing can be done, the device ID code, which is stored in GL.IDR, should be checked against device ID codes shown below to ensure that the correct device is being used. Current device ID codes are: DS3181 rev 1.0: o DS3182 rev 1.0: o DS3183 rev 1.0: o DS3184 rev 1 ...
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FF.RCR.RFRST = 1. Clear the FIFO Reset bits. FF.TCR.TFRST = 0. FF.RCR.RFRST = 0. Set the FIFO Transmit Level Control Register and the FIFO Transmit Port Address Control Register. Set the FIFO Receive Level Control Register and the FIFO Receive ...
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Considerations Select the HDLC Controller connection. The default setting connects it to the DS3/E3 Framers. Setting PORT.CR1.HDSEL = 1 connects the HDLC Controller to the PLCP framers. In POS-PHY mode, to select cell processing rather than packet processing, set PORT.CR2.PMCPE ...
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Packet Processor Monitoring the number of errored packets in the Packet Processor is recommended for proper operation. The REPC status bit is located in the PP.RSR Register and indicates when the errored packet count is not zero. An errored ...
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FUNCTIONAL DESCRIPTION 10.1 Processor Bus Interface 10.1.1 8/16-Bit Bus Widths The external processor bus can be sized for bits using the WIDTH pin. When in 8-bit mode (WIDTH=0), the address is composed of all the address ...
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See 10.1.6 Global Write Method All of ...
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Figure 10-1. Interrupt Structure SRL bit SRIE bit SRL bit SRIE bit SRL bit SRIE bit BLOCK LATCHED STATUS and INTERRUPT ENABLE REGISTERS Figure 10-1 not only tells the user how to determine which event caused the interrupt, it also ...
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Clocks 10.2.1 Line Clock Modes The system loopback (SLB) function does not affect the line clocks in any way. 10.2.1.1 Loop Timing Enabled When loop timing is enabled (PORT.CR3.LOOPT), the transmit clock source is the same as the receive ...
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LIU Enabled - CLAD Timing Enabled – this mode, the receive LIU sources the clock for the receive logic and one of the CLAD clocks sources the clock for the transmit logic. 10.2.1.2.3 LIU Disabled - ...
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Table 10-3 identifies the source of the output signal TLCLKn based on certain variables and register bits. Table 10-3. Source Selection of TLCLK Clock Signal LOOPT LBM[2:0] SIGNAL PORT.CR3 (PORT.CR4 TLCLKn ...
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Table 10-4. Source Selection of TCLKOn (internal TX clock) LOOPT SIGNAL PORT.CR3 TCLKOn Figure 10-3 shows the source of the RCLKOn signals. Figure 10-3. Internal RX Clock RLCLK Rx LIU CLOCK TCLKO Table 10-5 ...
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Line IO Pin Timing Source Selection The line IO pins can use any input clock pin (RLCLKn or TCLKIn) or output clock pin (TLCLKn, RCLKOn, or TCLKOn) for its clock pin and meet the AC timing specifications as long ...
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Table 10-7. Transmit Framer Pin Signal Timing Source Select LOOPT LBM[2:0] 1 XXX 1 XXX 1 XXX PLB (011) or DLB (100 ALB (001) 0 PLB (011) or DLB (100) 0 DLB&LLB (110) 0 LLB (010) 0 not ...
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Table 10-9. Receive Framer Pin Signal Timing Source Select LOOPT LBM[2:0] 1 XXX 1 XXX 1 XXX PLB (011) or DLB (100 ALB (001) 0 PLB (011) or DLB (100) 0 DLB&LLB (110) 0 LLB (010) 0 not ...
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Figure 10-4. Example IO Pin Clock Muxing TSER PIN INVERT TCLKI PIN INVERT RLCLK PIN INVERT RX LIU CLK CLAD CLOCKS DS3 CLK E3 CLK STS-1 CLK 10.2.5 Gapped Clocks The transmit and receive output clocks can be gapped in ...
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Reset and Power-Down The device can be reset at a global level via the GL.CR1.RST bit or the RST pin and at the port level via the PORT.CR1.RST bit and each port can be explicitly powered down via the ...
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Table 10-10. Reset and Power-Down Sources Register bit states - F0: Forced to 0, F1: Forced Set Set Don’t care Forced: Internally controlled Set: User controlled PIN REGISTER BITS 0 F0 ...
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After reset, the device will be in the default configuration:: The latched status bits are enabled to be cleared on write. The CLAD is disabled. The global 8KREF and one-second timers are disabled. The line interface is in B3ZS mode ...
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Figure 10-6. CLAD Block CLKA CLKB CLKC The clock rate adapter can also be disabled and all three clocks supplied externally using the CLKA, CLKB and CLKC pins as clock inputs. When the CLAD is disabled, the three reference clocks ...
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Table 10-11. CLAD IO Pin Decode GL.CR2 CLKA PIN CLAD[3: DS3 clock input 01 00 DS3 clock input 01 01 DS3 clock input 01 10 DS3 clock input 01 11 DS3 clock input clock input ...
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Table 10-12. Global 8 kHz Reference Source Table GL.CR2. GL.CR2. G8KIS G8KRS[2:0] 0 000 None, the 8KHZ divider is disabled. Derived from CLAD DS3 clock output or CLKA pin if CLAD 0 001 is disabled (Note: CLAD is disabled after ...
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One-Second Reference Generation The one-second-reference signal is used as an option to update the performance registers on a precise one- second interval. The generated internal signal should be about 50% duty cycle and it is derived from the Global ...
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Table 10-16. GPIO Port Alarm Monitor Select PORT.CR4 GPIO(A/B)[3:0] 0000 X 0001 X 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 X 1100 1101 X 1110 1111 X X 10.4.5 Performance Monitor Counter Update Details The performance monitor ...
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Figure 10-8. Performance Monitor Update Logic PORT.CR1.PMUM PORT.CR1.PMU GL.CR1.GPMU 00 GPIO8(GPMU) PIN 01 1X ONE SEC GL.CR1.GPM 10.4.6 Transmit Manual Error Insertion Transmit errors can be inserted in some of the functional blocks. These errors can be inserted using register ...
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Figure 10-9. Transmit Error Insert Logic PORT.CR.MEIMS PORT.CR.TMEI GL.CR1.MEIMS GL.CR1.TMEI GPIO6 PIN (TMEI) 10.5 Per-Port Resources 10.5.1 Loopbacks There are several loopback paths available. The following table lists the loopback modes available for analog loopback (ALB), line loopback (LLB), payload ...
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Figure 10-10 highlights where each loopback mode is located and gives an overall view of the various loopback paths available. Figure 10-10. Loopback Modes TAIS TUA1 B3ZS/ DS3/E3 HDB3 Transmit Encoder LIU DS3/E3 B3ZS/ Receive HDB3 Decoder LIU Clock Rate ...
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Line Loopback (LLB) Line loopback is enabled by setting PORT.CR4.LBM[2:0] = X10. DLB and LLB are enabled at the same time when LBM[2:0] = 110, and only LLB is enabled when LBM[2:0] = 010. The clock from the receive ...
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The DS3 framed AIS pattern is only available in DS3 modes. The unframed all ones pattern is available in all framing and clear-channel modes including the DS3 modes. The transmit line interface can send both ...
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Figure 10-12 shows the AIS signal flow through the device. Figure 10-12. AIS Signal Flow 0 TRANSMIT LINE 1 LLB LINE/TRIBUTARY SIDE RECEIVE LINE Table 10-18 lists the LAIS decodes for various line AIS enable modes. Table 10-18. Line AIS ...
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Table 10-19 lists the PAIS decodes for various payload AIS enable modes. Table 10-19. Payload (Downstream) AIS Enable Modes PAIS[2:0] WHEN AIS IS SENT PORT.CR1 000 Always 001 When LLB (no DLB) active 010 When PLB active 011 When LLB(no ...
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Fractional Payload Controller The Fractional Payload Controller allows the user flexibility to control sub-rate datastreams. The Fractional Payload Controller performs fractional overhead/payload data multiplexing. Fractional overhead is sourced from either an internal register or the external interface. The allocation ...
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Table 10-22. TPDENIn/TPOHENn/TFOHENIn Input Pin Functions TPFPE FM[5:0] PORT.CR2 PORT.CR3 0XX00X (FRM) X 0XX010 (IFRAC) X 0XX011 (XFRAC) X 0XX10X (PLCP) 0 0XX10X (PLCP) 1 0XX110 (FFRAC) X 1XXXXX (CLR) X Table 10-23. TSOFOn/TDENn/TPOHSOFn/TFOHENOn Output Pin Functions TPFPE FM[5:0] PORT.CR2 ...
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Table 10-24. TCLKOn/TGCLKn/TPOHCLKn Output Pin Functions FM[5:0] TPFPE PORT.CR2 PORT.CR3 0XX00X (FRM) 0 0XX00X (FRM) 1 0XX00X (FRM) 1 0XX010 (IFRAC) 0 0XX010 (IFRAC) 1 0XX010 (IFRAC) 1 0XX011 (XFRAC) X 0XX10X (PLCP) 0 0XX10X (PLCP) 1 0XX10X (PLCP) 1 ...
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Table 10-27. RSERn/RPOHn Output Pin Functions FM[5:0] RPFPE PORT.CR2 PORT.CR3 0XX00X (FRM) 0 0XX00X (FRM) 1 0XX010 (IFRAC) 0 0XX010 (IFRAC) 1 0XX011 (XFRAC) X 0XX10X (PLCP) 0 0XX10X (PLCP) 1 0XX110 (FFRAC) X 1XX0XX (CLR) 0 1XX0XX (CLR) 1 ...
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Table 10-30. RSOFOn/RDENn/RPOHSOFn/RFOHENOn Output Pin Functions FM[5:0] RPFPE PORT.CR2 PORT.CR3 0XX00X (FRM) 0 0XX00X (FRM) 1 0XX00X (FRM) 1 0XX010 (IFRAC) 0 0XX010 (IFRAC) 1 0XX011 (XFRAC) X 0XX011 (XFRAC) X 0XX10X (PLCP) 0 0XX10X (PLCP) 1 0XX110 (FFRAC) X ...
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Framing Modes The framing modes are selected independently of the line interface modes using the PORT.CR2.FM[5:0] control bits. Different blocks are used in different framing modes. The bit error test (BERT) function can be enabled in any mode. The ...
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Mapping Modes Cells and packets are mapped into various internally generated frame structures or mapped with no framing or mapped into an externally generated frame structure. When ATM cells are mapped into an internally generated frame structure they are ...
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Figure 10-14. DS3 PLCP Frame A1 A2 P11 P10 ...
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Figure 10-15. DS3 M23 (with C-Bits Used as Payload) Frame 84 169 bits 11 bits ...
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Figure 10-17. E3 PLCP Frame ...
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Figure 10-19. E3 G.832 Frame FA1 FA2 10.5.12 Line Interface Modes The line interface modes can be selected semi-independently of the framing modes using the PORT.CR2.LM[2:0] control bits. The major blocks controlled are the transmit ...
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Table 10-33. Line Mode Select Bits LM[2:0] LINE.TCR.TZSD LM[2:0] AND (PORT.CR2) LINE.RCR.RZSD 0 000 0 001 0 010 0 011 1 000 1 001 1 010 1 011 X 1XX LINE CODE LIU B3ZS/HDB3 OFF B3ZS/HDB3 ON B3ZS/HDB3 ON B3ZS/HDB3 ...
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UTOPIA/POS-PHY/SPI-3 System Interface 10.6.1 General Description The UTOPIA/POS-PHY system interface transports ATM cells or HDLC packets between the DS318x and an ATM or Link Layer device. In UTOPIA mode, the DS318x is connected to an ATM layer device and ...
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... Transfer th (n-1) Transfer th n Transfer Bit 0 Byte 2 Byte 1 Byte 6 Byte 5 • • • • • • Byte 4n-6 Byte 4n-7 Byte 4n-2 Byte 4n-3 135 DS3181/DS3182/DS3183/DS3184 st 1 Transfer nd 2 Transfer th (n-1) Transfer th n Transfer st 1 Transfer nd 2 Transfer th (n-1) Transfer th n Transfer ...
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... The Receive System Interface Bus Controller accepts a receive clock (RSCLK), receive address (RADR[4:0]), and receive enable (REN). It outputs a receive data bus consisting of receive data (RDATA[31:0]), receive parity (RPRTY), and receive start of cell (RSOX), as well as, receive direct cell available (RDXA) and receive polled cell st 1 Transfer nd 2 Transfer th (n-1) Transfer th n Transfer 136 DS3181/DS3182/DS3183/DS3184 ...
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The receive bus is used to transfer cell data whenever one of the ports is selected for cell data transfer. RSOX is asserted during the first transfer of a cell, cell data is transferred on RDATA, and ...
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It outputs transmit direct packet available (TDXA), transmit polled packet available (TPXA), and transmit selected packet available (TSPA) signals. The transmit bus is used to transfer packet data whenever one of the ports is selected for packet data ...
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When the maximum burst length has been transferred, data transfer will continue from the same port if no other port has data ...
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ATM Cell Processor • Programmable HEC insertion and extraction – The transmit side can be programmed to accept cells from the system interface that not contain a HEC byte. If cells are transferred without a HEC ...
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Receive Cell/Packet Processor The Receive Cell Processor and Receive Packet Processor both receive the incoming data stream from the Receive Framer (minus all overhead and stuff data), however, only one of the processors will be enabled. The other will ...
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Cell scrambling is programmable (payload, entire data stream, or DSS). If cell processing is disabled, the entire data stream will be scrambled whenever scrambling is enabled Once all cell processing has been completed, in bit synchronous ...
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Figure 10-26. Receive DSS Scrambler Synchronization State Diagram Steady 8 Cells Fail Verification Verification 32 Samples Loaded If cell processing is disabled, a cell boundary is arbitrarily chosen, and the data is divided into "cells" whose size is programmable. If ...
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DS3 Clear-Channel—OHM; STS-1 Clear-Channel—OHM; and E3 Clear-Channel—OHM modes. In bit synchronous mode, the serial data stream is demultiplexed into an 8-bit parallel data stream (as determined by the data path ...
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HEC, HEC error monitoring transitions to the “Detection” state. In the “Detection” state, good cells are passed on. Cells received with one or more errors are considered errored cells cells are received with a ...
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Figure 10-30. Cell Format for 52-Byte Cell With 32-Bit Data Bus Bit 31 Header 1 Payload 1 Payload 5 • • • Payload 41 Payload 45 10.7.6 Packet Processor 10.7.6.1 Transmit Packet Processor The Transmit Packet Processor accepts data from ...
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Inter-frame padding inserts start flags, end flags and inter-frame fill between packets. There will be at least one flag plus a programmable number of additional flags between packets. In octet aligned mode, the inter-frame fill is flags. In bit synchronous ...
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In octet aligned mode, after destuffing is completed, the 8-bit parallel data stream is passed on to packet size checking. If packet processing is disabled, destuffing is ...
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FIFO overflow condition is declared. If any other packet data is received while full, the current packet being transferred is marked with an abort indication, and a FIFO overflow condition is ...
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DS3/E3 PLCP Framer 10.8.1 General Description The PLCP Framer demaps the ATM cells from the DS3/E3 PLCP data stream in the receive direction and maps ATM cells into the DS3/E3 PLCP data stream in the transmit direction. The receive ...
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Transmit PLCP Frame Processor The Transmit PLCP Frame Processor receives the ATM cells from the ATM/Packet Processor performs trailer generation, framing generation, error insertion, and overhead insertion. The bits in a byte are transmitted MSB first, LSB last. When ...
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Figure 10-32. DS3 PLCP Frame Format A1 A2 P11 P10 ...
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Transmit DS3 PLCP Frame Generation DS3 PLCP frame generator receives the incoming PLCP payload data stream, and overwrites all of the overhead byte locations. The first two bytes of each sub-frame are overwritten with the frame alignment bytes A1 ...
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Error insertion can be initiated by a register bit (PLCP.TEIR.TSEI) or initiated by the manual error insertion input (TMEI). Each error type is individually enabled by a register bit. The error insertion initiation type (register or input) is programmable. Once ...
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A Change Of Frame Alignment (COFA) is declared when the DS3 PLCP framer updates the data path frame counters with a frame alignment that is different from the current data path frame alignment. A Remote Alarm Indication (RAI) condition is ...
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Figure 10-34. E3 PLCP Frame Format ...
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The fourth byte of sub-frame 5 is overwritten with the F1 byte from the corresponding register or the trail trace byte input from the transmit trail trace controller. The F1 byte from the corresponding register, the trail trace byte input ...
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Receive E3 PLCP Frame Processor The Receive E3 PLCP Frame Processor performs E3 PLCP framing, byte destuffing, performance monitoring and overhead extraction. The E3 PLCP frame format is shown in value of F6h and 28h respectively. P8 – P0 ...
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The detection of POI byte (P#) framing errors is programmable (on or off). BIP-8 errors are determined by calculating the BIP-8 of the current frame (path overhead and cell bytes), ...
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Fractional Payload Controller 10.9.1 General Description The Fractional Payload Controller uses a fraction of the DS3/E3 payload for ATM cell or HDLC packets. The unused DS3/E3 payload is considered fractional overhead and can be used as a proprietary data ...
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Transmit Fractional Interface The Transmit Fractional Interface receives the payload data stream from the ATM/Packet Processor and inserts a fractional overhead stream. The incoming fractional overhead stream consists of fractional overhead (TFOHn), input fractional overhead enable (TFOHENIn), and output ...
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Figure 10-37. Data Group Format Data Group (g bits) Section A (a bits) Figure 10-38. Frame Format Data Group Data Group Data Group Section B (g-a bits) Frame (f bits) • • • Data Group Data Group 162 Data Group ...
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DS3/E3 Framer/Formatter 10.10.1 General Description The Receive DS3/E3 Framer receives a unipolar DS3/E3 signal, determines frame alignment and extracts the DS3/E3 overhead in the receive direction. The Transmit DS3/E3 Formatter receives a DS3/E3 payload, generates framing, inserts DS3/E3 overhead, ...
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Arbitrary framing format support – Accepts a signal with an arbitrary framing format. The Line overhead/stuff periods are removed from the data stream using an overhead mask signal. • Detects alarms and errors – Detects DS3 alarm conditions (SEF, ...
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The multiframe boundary is found by identifying the multiframe alignment bits M framer is an off-line framer that only updates the data path frame counters when either an out of ...
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Figure 10-41. DS3 Sub-Frame Framer State Diagram All 4 bit positions failed Verify 2 F-bits loaded The multiframe framer checks for a multiframe boundary. When the multiframe framer identifies a multiframe boundary, it updates the data path frame counters if ...
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Figure 10-42. DS3 Multiframe Framer State Diagram Verify If multiframe alignment OOF is disabled, an Out Of Frame (OOF) condition is declared when three or more out of the last 16 consecutive sub-frame alignment bits (F-bits) have been errored, or ...
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AIS signal is absent, and it is reset when an AIS signal is absent for consecutive DS3 frames. An AIS condition is terminated when an AIS signal is absent for consecutive DS3 frames. A ...
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Table 10-34. C-Bit DS3 Frame Overhead Bit Definitions BIT DEFINITION Remote Defect Indication (RDI Parity Bits and M Multiframe Alignment Bits Sub-frame ...
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The bit C is overwritten with the Far-End Alarm and Control (FEAC) data input from the transmit FEAC controller. 13 The bits and C are all overwritten with the calculated payload parity from the previous DS3 ...
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output DS3 frame. And 10.10.5.5.1 Receive C-bit DS3 Frame Format The DS3 frame format is shown in referred to as the far-end SEF/AIS bits). P ...
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Transmit M23 DS3 Frame Generation M23 DS3 frame generation receives the incoming payload data stream, and overwrites the entire DS3 overhead bit locations. The multiframe alignment bits (M respectively. The sub-frame alignment bits (F (1001) respectively. The X-bits (X ...
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Transmit M23 DS3 AIS/Idle Generation M23 DS3 AIS/Idle generation overwrites the data stream with AIS or an Idle signal. If transmit Idle is enabled, the data stream payload is forced to an 1100 pattern with two ones immediately following ...
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G.751 E3 Framer/Formatter 10.10.7.1 Transmit G.751 E3 Frame Processor The G.751 E3 frame format is shown in bit used to indicate the presence of an alarm to the remote terminal equipment the National use bit reserved for ...
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Transmit G.751 E3 Overhead Insertion Overhead insertion can insert any (or all) of the E3 overhead bits into the E3 frame. The FAS, A bit, and N bit can be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, ...
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A word error increments the count once for each FAS that does not match its expected value ( per frame). The receive alarm indication (RAI) signal is high ...
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Figure 10-45. MA Byte Format MSB 1 RDI REI SL SL RDI - Remote Defect Indicator REI - Remote Error Indicator SL - Signal Label MI - Multi-frame Indicator TM - Timing Marker Table 10-36 shows the function of each ...
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The payload type is sourced from a register. The three register bits are inserted in the third, ...
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Transmit G.832 E3 AIS Generation G.832 E3 AIS generation overwrites the data stream with AIS. If transmit AIS is enabled, the data stream (payload and E3 overhead) is forced to all ones. 10.10.8.6 Receive G.832 E3 Frame Processor The ...
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Parity errors are determined by calculating the BIP-8 (8-Bit Interleaved Parity) of the current E3 frame (overhead and payload bytes), and comparing the calculated BIP-8 to the EM byte in the next frame. The type of parity errors accumulated is ...
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The NR byte is integrated and stored in a register along with a change indication sent to the receive FEAC controller, and it can be sent to the receive HDLC controller. The byte sent to the receive HDLC ...
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See Figure 10-46 for the location of HDLC controllers within the DS318x devices. Figure 10-46. HDLC Controller Block Diagram TAIS TUA1 B3ZS/ DS3/E3 HDB3 Transmit Encoder LIU DS3/E3 B3ZS/ Receive HDB3 LIU Decoder Clock Rate Adapter 10.11.2 Features • Programmable ...
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FIFO contains less than two bytes or transmit packet start is disabled. Transmit packet start is programmable (on or off). When the Transmit Packet Processor reads the Transmit FIFO while it is empty, the output data stream is marked with ...
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Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag abort sequence is detected, the packet is marked with an abort indication, and all subsequent data is discarded until ...
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The data is forced to all ones during LOS, LOF and AIS detection to eliminate false messages The transmit direction inputs the trace identifier data from the ...
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Transmit Data Storage The Transmit Data Storage block contains memory for 16 bytes of data and controller circuitry for reading and writing the memory. The Transmit Data Storage controller functions include filling the memory and maintaining the memory read ...
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... The data is read from the Receive Data Storage via the microprocessor interface. The Receive Data Storage contains the current trail trace identifier, the receive trail trace identifier, and the expected trail trace identifier. Bit 4 Bit 5 Bit 6 DT[4] DT[5] DT[6] Figure 10-48) of each trail trace identifier byte (The 187 DS3181/DS3182/DS3183/DS3184 Bit 7 Bit 8 LSB DT[7] DT[8] ...
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FEAC Controller 10.13.1 General Description The FEAC Controller demaps FEAC codewords from a DS3/E3 data stream in the receive direction and maps FEAC codewords into a DS3/E3 data stream in the transmit direction. The transmit direction demaps FEAC codewords ...
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Transmit FEAC Processor The Transmit FEAC Processor accepts data from the Transmit Data Storage performs FEAC processing. The FEAC codes are read from Transmit Data Storage with the MSB (C[1]) in TFCA[0] or TFCB[0], and the LSB (C[6]) in ...
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Line Encoder/Decoder 10.14.1 General Description The B3ZS/HDB3 Decoder converts a bipolar signal to a unipolar signal in the receive direction. B3ZS/HDB3 Encoder converts a unipolar signal to a bipolar signal in the transmit direction. In the transmit direction, the ...
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Zero suppression encoding converts an AMI bipolar data stream into a B3ZS or HDB3 encoded bipolar data stream. A B3ZS encoded bipolar signal is generated by inserting a B3ZS signature into the bipolar data stream if both the POS and ...
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Figure 10-53. Zero suppression decoding is also programmable (on or off). Note: Immediately after a reset or a LOS condition, the first B3ZS/HDB3 signature to be detected will not depend upon the polarity of any BPV contained within the signature. ...
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Note: Immediately after a reset (or datapath reset LOS condition, a BPV will not be declared when the first valid one (RPOS high and RNEG low, or RPOS low and RNEG high) is received. Bipolar to unipolar conversion ...
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Table 10-38. Pseudorandom Pattern Generation PATTERN TYPE PTF[4:0] (hex O.153 (511 type O.152 and O.153 08 (2047 type O.151 O.153 O.151 QRSS ...
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Receive PRBS Synchronization PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and then checking the next ...
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Figure 10-56. Repetitive Pattern Synchronization State Diagram 1 bit error Verify Pattern Matches 10.15.4.3 Receive Pattern Monitoring Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An Out ...
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Line Interface Unit (LIU) 10.16.1 General Description The line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit paths and a built-in ...
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Detailed Description The receiver performs clock and data recovery from an alternate mark inversion (AMI) coded signal or a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal. The transmitter drives standard pulse-shape waveforms onto ...
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Interfacing to the Line The transmitter interfaces to the outgoing DS3/E3/STS-1 coaxial cable (75Ω) through a 2:1 step-down transformer connected to the TXPn and TXNn pins. recommended interface components. 10.16.4.4 Transmit Driver Monitor If the transmit driver monitor detects ...
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Table 10-41. Recommended Transformers MANUFACTURER PART Pulse Engineering PE-65968 Pulse Engineering PE-65969 TG07- Halo Electronics 0206NS TD07- Halo Electronics 0206NE Note: Table subject to change. Industrial temperature range and multiport transformers are also available. Contact the manufacturers for details at ...