DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 134

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6 UTOPIA/POS-PHY/SPI-3 System Interface
10.6.1 General Description
The UTOPIA/POS-PHY system interface transports ATM cells or HDLC packets between the DS318x and an ATM
or Link Layer device. In UTOPIA mode, the DS318x is connected to an ATM layer device and cells are transported
via a UTOPIA L2 or UTOPIA L3 Bus. In POS-PHY packet mode, the DS318x is connected to a Link Layer device
and the packets are transported via a POS-PHY 2 or a POS-PHY 3 (or SPI-3) Bus. In POS-PHY cell mode, the
DS318x is connected to an ATM layer device and cells are transported via a POS-PHY 2 or a POS-PHY 3 (or SPI-
3) Bus. The system interface supports 8-bit, 16-bit, or 32-bit transfers at a rate of 66MHz or less.
The receive direction removes cell/packet data for each port from the FIFO, and outputs the cell/packet data to the
ATM/Link Layer device via the system interface.
The transmit direction inputs the cell/packet data from the ATM/Link Layer device via the system interface, and
stores the cell/packet data for each port in the FIFO.
See
Figure 10-20. System Interface Functional Diagram
10.6.2 Features
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•
•
•
•
Clock Rate
Programmable system interface type – When performing cell mapping/demapping, the system interface can
be programmed as a UTOPIA Level 2 Bus, a UTOPIA Level 3 Bus, a POS-PHY Level 2 Bus, or a POS-PHY
Level 3 (or SPI-3) Bus. When performing packet mapping/demapping, the system interface can be
programmed as a POS-PHY Level 2 Bus or a POS-PHY Level 3 (or SPI-3) Bus.
Selectable system interface bus width – The data bus can be a 32-bit, 16-bit, or 8-bit bus at operations
speeds up to 66 MHz.
Supports multiple ports on the system interface – Each line has its own port address for access via the
system interface.
Supports per-port system loopback – Each port can be placed in system loopback which causes
cells/packets from the transmit FIFO to be looped back to the receive FIFO.
System interface byte reordering – In 16-bit and 32-bit modes, the received/transmitted order of the bytes
transferred across the system interface is programmable. i.e., the first byte received/transmitted by ATM cell /
packet processing can be transferred in [31:24] ([15:8]) or [7:0].
Receive
Transmit
DS3/E3
Figure 10-20
DS3/E3
Adapter
LIU
LIU
for the location of the system interface block in the DS318x devices.
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
IEEE P1149.1
Access Port
JTAG Test
FEAC
DS3 / E3
Receive
Framer
Formatter
DS3 / E3
Transmit
Buf f er
Trace
Trail
HDLC
UA1
GEN
134
TX FRAC/
PLCP
RX FRAC/
PLCP
Processor
Processor
Rx Packet
Processor
Processor
Tx Packet
RX BERT
TX BERT
Rx Cell
Tx Cell
Microprocessor
Interface
FIFO
FIFO
Tx
Rx