DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 17

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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The following sections describe the features provided by the DS3181 (single), DS3182 (dual), DS3183 (triple), and
DS3184 (quad) PHYs.
3.1 Global Features
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3.2 Receive DS3/E3/STS-1 LIU Features
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3.3 Receive DS3/E3 Framer Features
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System interface configurable for UTOPIA L2/UTOPIA L3 for ATM cell traffic or POS-PHY L2/POS-PHY L3 or
SPI-3 for HDLC packets or mixed packet/cell traffic
Supports the following transmission protocols:
In UTOPIA bus mode, ports are independently configurable for any ATM protocol
In POS-PHY bus mode, ports are independently configurable for any ATM or HDLC protocol
Programmable to support internally or externally controlled sub-rate DS3 or E3 on any ports
Supports gapped 52 MHz clock rates for signals embedded in SONET/SDH
Optional transmit loop timed clock(s) mode using the associated port’s receive clock(s)
Optional transmit clock mode using references generated by the internal Clock Rate Adapter (CLAD)
Requires only a single reference clock for all three LIU data rates using internal CLAD
The LIU can be powered down and bypassed for direct logic IO to/from line circuits.
Jitter attenuator can be placed in either transmit or receive path when the LIU is enabled.
Clock, data and control signals can be inverted for a direct interface to many other devices
Detection of loss of transmit clock and loss of receive clock
Automatic one-second, external or manual update of performance monitoring counters
Each port can be placed into a low-power standby mode when not being used
Framing and line code error insertion available
AGC/Equalizer block handles from 0 dB to 15 dB of cable loss
Loss-of-lock PLL status indication
Interfaces directly to a DSX monitor signal (20 dB flat loss) using built-in pre-amp
Digital and analog Loss of Signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Per-channel power-down control
Frame synchronization for M23 or C-bit Parity DS3, or G.751 E3 or G.832 E3
B3ZS/HDB3/AMI decoding
Detection and accumulation of bipolar violations (BPV), code violations (CV), excessive zeroes occurrences
(EXZ), F-bit errors, M-bit errors, FAS errors, LOF occurrences, P-bit parity errors, CP-bit parity errors, BIP-8
errors, and far end block errors (FEBE)
FEATURE DETAILS
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Direct-mapped ATM over DS3 or sub-rate DS3
PLCP-mapped ATM over DS3
Direct-mapped ATM over G.751 E3 or sub-rate G.751 E3
PLCP-mapped ATM over G.751 E3
Direct-mapped ATM over G.832 E3 or sub-rate G.832 E3
Bit or byte synchronous (octet aligned) direct-mapped ATM over externally-defined frame formats up to
52 Mbps
Clear-channel ATM (cell-based physical layer) at line rates up to 52 Mbps
Clear-channel ATM DSS at line rates up to 52 Mbps
Direct-mapped HDLC over DS3 or sub-rate DS3
Direct-mapped HDLC over G.751 E3 or sub-rate G.751 E3
Direct-mapped HDLC over G.832 E3 or sub-rate G.832 E3
Bit or byte synchronous (octet aligned) direct-mapped HDLC over externally-defined frame formats up
to 52 Mbps
Clear-channel HDLC at line rates up to 52 Mbps
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