DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 229

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.2 Receive System Interface Register Map
The receive system interface block has three registers.
Table 12-22. Receive System Interface Register Map
12.3.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 10 to 8: Receive System RVAL Minimum Deassertion Time (RMDT[2:0]) – These three bits indicate the
minimum number of clock cycles that RVAL must remain deasserted between packets transferred from the same
port, a transfer of data equal to the maximum burst depth length (if enabled), or before RSX can be asserted. A
value of zero, means that RVAL will not deassert between packets transferred from the same port or between
transfers of the maximum burst length when no other port has data available. These bits are ignored in UTOPIA
and POS-PHY Level 2 modes. Note: The RVAL minimum deassertion time is for optionally extending the time
between packet transfers and port changes to allow a POS-PHY Level 3 Link Layer device enough time to
deassert REN and pause the next data transfer.
Bits 6 to 4: Receive Cell Available Deassertion Time (RXAD[2:0]) – These three bits indicate the number of
transfers that will occur after the selected Receive FIFO indicates it is "empty". A value of 000, enables the default
mode. The default for UTOPIA Level 2 is 0 (RDXA will transition low on the clock edge following the clock edge that
outputs payload byte 48 in 8-bit mode, payload bytes 47 and 48 in 16-bit mode, and payload bytes 45, 46, 47, and
48 in 32-bit mode). The default for UTOPIA Level 3 is for RDXA to transition low on the clock edge that outputs the
start of cell. These bits are ignored in POS-PHY mode.
Bit 3: Receive System Parity Polarity (RPARP) – When 0, the RPRTY signal will maintain odd parity (for all 0''s,
RPRTY is high). When 1, the RPRTY signal will maintain even parity (for all 0''s, RPRTY is low).
Bit 2: Receive System Fill Level Inversion (RFLVI) – When 0, the polarity of the RPXA and RDXA signals will be
normal (high for data available). When 1, the polarity of the RPXA and RDXA signals will be inverted (low for data
available).
Bit 1: Receive System Interface Byte Reordering Enable (RSBRE) – When 0, byte reordering is disabled, and
the first byte received is transferred across the system interface as the most significant byte (RDATA[31:24] in 32-
bit mode or RDATA[15:8] in 16-bit mode). When 1, byte reordering is enabled, and the first byte received is
transferred across the system interface as the least significant byte (RDATA[7:0]).
Bit 0: Receive System HEC Transfer Enable (RHECT) – When 0, The HEC byte is not transferred across the
receive system interface. When 1, the HEC byte is transferred across the receive system interface with the cell
data.
ADDRESS
03Ch
038h
03Ah
03Eh
15
—
—
0
7
0
REGISTER
SI.RCR1
SI.RCR2
SI.RSRL
—
RXAD2
14
—
0
6
0
SI.RCR1
System Interface Receive Control Register 1
038h
System Interface Receive Control Register 1
System Interface Receive Control Register 2
System Interface Receive Status Register Latched
Unused
RXAD1
13
—
0
5
0
REGISTER DESCRIPTION
RXAD0
12
—
0
0
4
229
RPARP
11
—
0
3
0
RMDT2
RFLVI
10
0
2
0
RMDT1
RSBRE
9
0
1
0
RMDT0
RHECT
8
0
0
0