DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 67

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-2. TX Line IO HDB3 Functional Timing Diagram
8.3.1.2
There is no suggested time alignment between the RXPn, RXNn and RX LINE signals and the RLCLKn clock
signal. The RX DATA signal is not an always readily available signal, it is meant to represent the data value of the
other signals.
The RXPn and RXNn pins are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU is enabled.
The RPOSn, RNEGn and RLCLKn pins are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU
is disabled.
The RPOSn and RNEGn signals are sampled at the rising edge of the reference clock signal if the clock pin is not
inverted; otherwise they are sampled at the negative edge. The RLCLKn clock pin is the clock reference used for
the RPOSn and RNEGn signals. The RPOSn and RNEGn pins can be inverted.
RXPn and RXNn are differential analog input pins. They are biased around ½ VDD and pulse above and below the
bias voltage by about 1 Volt with zero cable length. These signals are connected to the windings of a 1:2 step up
transformer and the other winding of the transformer is connected to the RX LINE signal. The RX LINE signal is a
bipolar signal that pulses about 1 Volt positive and 1 Volt negative above and below ground (0 volts) with zero
cable length. See
Figure 8-3
Figure 8-3. RX Line IO B3ZS Functional Timing Diagram
(TX DATA)
(RX DATA)
(TX LINE)
(RX LINE)
TLCLK
RLCLK
TNEG
TPOS
RPOS
RNEG
TXN
TXP
RXP
RXN
B3ZS/HDB3/AMI Mode Receive Pin Functional Timing
and
Figure 8-4
0 V
0 V
BIAS V
BIAS V
Figure 1-1
+
+
shows the relationship between the analog and the digital outputs.
-
-
for a diagram of the external connections.
B
B
B
B
B
B
B
B
V
V
V
V
67
V
V
V
V
HDB3 CODEWORD
B3ZS CODEWORD