DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 30

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DS3181

Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3181

Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3181+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3181N+
Manufacturer:
Maxim Integrated
Quantity:
10 000
6.5 DS3/E3 Flexible External Fractional (Subrate) Mode Configuration Mode
DS3/E3 Flexible External Fractional Mode allows subrate datastreams to be inserted into a DS3 or E3 line, with the
fractional overhead and payload externally multiplexed. Major functional blocks for the DS3/E3 Flexible External
Fractional Mode are shown in
in
The “-OHM” modes are not allowed in fractional framing modes since the user cannot distinguish between internal
framing overhead and external framing overhead bit locations.
Table 6-5. DS3/E3 Flexible External Fractional (Subrate) Mode Configuration Registers
UTOPIA L2 ATM
UTOPIA L3 ATM
POS-PHY L2 ATM
POS-PHY L3 ATM
POS-PHY L2 Packet
POS-PHY L3 Packet
Figure 6-5. DS3/E3 Flexible External Fractional Mode
TOHMOn
RLCLKn
RNEGn/
ROHMIn
RPOSn/
TNEGn/
TLCLKn
TPOSn/
RLCVn/
RDATn
TDATn
RXPn
RXNn
Table
TXPn
TXNn
6-5.
MODE
Clock Rate
Receive
Transmit
DS3/E3
DS3/E3
Adapter
LIU
LIU
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
FM[5:0]
0XX110
0XX110
0XX110
0XX110
0XX110
0XX110
Figure
TUA1
TAIS
6-5. Mapping configuration is programmable on per-port basis and is shown
SIM[1:0]
GL.CR1
IEEE P1149.1
Access Port
JTAG Test
FEAC
00
01
10
11
10
11
Formatter
DS3 / E3
DS3 / E3
Receive
Transmit
Framer
Buffer
Trace
Trail
HDLC
PORT.CR2
PMCPE
30
GEN
UA1
X
X
1
1
0
0
RX BERT
TX BERT
Processor
Tx Packet
Processor
Rx Packet
Processor
Processor
Rx Cell
Tx Cell
Microprocessor
Interface
FIFO
FIFO
Tx
Rx
Interface
n = port # (1-4)
System

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