DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 65

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AVDDRn
AVDDTn
AVDDJn
AVDDC
JTCLK
JTRST
CLKC
JTMS
JTDO
CLKA
CLKB
JTDI
VDD
VSS
PIN
TYPE
PWR
PWR
PWR
PWR
PWR
PWR
Ipu
Ipu
Ipu
Oz
IO
IO
I
I
JTAG Clock
JTCLK: This clock input is typically a low frequency (less than 10 MHz) 50% duty
cycle clock signal.
JTAG Mode Select (with pullup)
JTMS: This input signal is used to control the JTAG controller state machine and is
sampled on the rising edge of JTCLK.
JTAG Data Input (with pullup)
JTDI: This input signal is used to input data into the register that is enabled by the
JTAG controller state machine and is sampled on the rising edge of JTCLK.
JTAG Data Output
JTDO: This output signal is the output of an internal scan shift register enabled by the
JTAG controller state machine and is updated on the falling edge of JTCLK. The pin
is in the high impedance mode when a register is not selected or when the JTRST
signal is high. The pin goes into and exits the high impedance mode after the falling
edge of JTCLK
JTAG Reset (active low with pullup)
JTRST: This input forces the JTAG controller logic into the reset state and forces the
JTDO pin into high impedance when low. This pin should be low while power is
applied and set high after the power is stable. The pin can be driven high or low for
normal operation, but must be high for JTAG operation.
Clock A
CLKA: This clock input is a DS3 signal (44.736MHz ±20ppm) when the CLAD is
disabled or it is one of the CLAD reference clock signals when the CLAD is enabled.
Clock B
CLKB: This pin is a E3 (34.368 MHz ±20 ppm) input signal when the CLAD is
disabled (reset default) or it can be enabled to output a generated clock when the
CLAD is enabled. The pin is driven low when it is not selected to output a clock signal
and the CLAD is enabled. See
Clock C
CLKC: This pin is a STS-1 (51.84 MHz ±20ppm) input signal when the CLAD is
disabled or it can be enabled to output a generated clock when the CLAD is enabled.
The pin is driven low when it is not selected to output a clock signal and the CLAD is
enabled. See
Ground, 0V potential. Common to digital core, digital IO and all analog circuits.
Digital 3.3V. Common to digital core and digital IO.
Analog 3.3V for receive LIU on port n. Powers receive LIU on port n.
Analog 3.3V for transmit LIU on port n. Powers transmit LIU on port n.
Analog 3.3V for jitter attenuator on port n. Powers jitter attenuator on port n.
Analog 3.3V for CLAD. Powers clock rate adapter common to all ports.
Table
10-11.
POWER
CLAD
JTAG
65
Table
FUNCTION
10-11.