DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 340

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 15: Manual Error Insert Mode Select (MEIMS) – When 0, the transmit manual error insertion signal (TMEI)
will not cause errors to be inserted. When 1, TMEI will causes an error to be inserted when it transitions from a 0 to
a 1. Note: Enabling TMEI does not disable error insertion using TCER[6:0] and TCEN[7:0].
Manual error insertion is available at the global level, but not on a per-port basis for the cell processor.
(PORT.CR1.MEIM must be set for global error insertion to insert a packet error.)
Bits 14 to 8: Transmit Errored Cell Insertion Rate (TCER[6:0]) – These seven bits indicate the rate at which
errored cells are to be output. One out of every x * 10
TCER[6:4] is the value y, which has a maximum value of 6. If TCER[3:0] has a value of 0h errored cell insertion is
disabled. If TCER[6:4] has a value of 6xh or 7xh the errored cell rate will be x * 10
results in every cell being errored. A TCER[6:0] value of 0Fh results in every 15
value of 11h results in every 10
with a TCER[3:0] value that is non-zero. If the TECC register is written to during the middle of an errored cell
insertion process, the current process is halted, and a new process will be started using the new values of
TCER[6:0] and TCEN[7:0}. Errored cell insertion ends when TCEN[7:0] errored cells have been transmitted.
Bits 7 to 0: Transmit Errored Cell Insertion Number (TCEN[7:0]) – These eight bits indicate the total number of
errored cells to be transmitted. A value of FFh results in continuous errored cell insertion at the specified rate.
TCER[3:0] - X
Fh
0h
1h
1h
1h
1h
MEIMS
TCEN7
15
0
7
0
TCER6
TCEN6
14
0
6
0
th
CP.TECC
Cell Processor Transmit Errored Cell Control Register
(1,3,5,7)A4h
cell being errored. Errored cell insertion starts when the TECC register is written
TCER[6:4] - Y
TCER5
TCEN5
XXh
0Xh
0Xh
1Xh
6Xh
7Xh
13
0
5
0
TCER4
TCEN4
y
12
0
0
4
340
cells is to be an errored cell. TCER[3:0] is the value x, and
TCER3
TCEN3
TCER[6:0]
11
0
3
0
X0h
0Fh
01h
11h
61h
71h
TCER2
TCEN2
10
0
2
0
th
cell being errored. A TCER[6:0]
6
. A TCER[6:0] value of 01h
ERROR RATE (x * 10
TCER1
TCEN1
1 out of 10
1 out of 10
1 out of 15 cells
1 out of 10 cells
9
0
1
0
1 out of 1 cells
DISABLED
TCER0
TCEN0
6
6
cells
cells
8
0
0
0
y )