DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 98

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DS3181

Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3181

Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Maxim Integrated
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Figure 10-1. Interrupt Structure
Figure 10-1
enable a particular interrupt. Each block has a Status Register Interrupt Enable register that must be set in order to
enable an interrupt. The next step is to unmask the interrupt at the port level, on a per-port basis. This is controlled
in the Global Interrupt Status Register Interrupt Enable register (GL.ISRIE). Now the device is ready to drive the
INT pin low when a particular status bit gets set.
For example, in order to enable DS3 Out of Frame interrupts on Port 2, the following registers would need to be
written:
Register bit
T3.RSRIE1.OOFIE
GL.ISRIE.PISRIE2
The following status registers bits will be set upon reception of OOF on Port 2:
Register bit
T3.RSRL1.OOFL
PORT.ISR.FMSR
GL.ISR.PISR2
BLOCK LATCHED
STATUS and
INTERRUPT
ENABLE
REGISTERS
SRIE bit
SRIE bit
SRIE bit
SRL bit
SRL bit
SRL bit
not only tells the user how to determine which event caused the interrupt, it also tells the user how to
Address
0x32C
0x012
Address
0x328
0x250
0x010
Value Written
0x0002
0x0020
Value Read
0x0002
0x0001
0x0020
PORT INTERRUPT
STATUS
REGISTER
PORT.ISR bit
98
Note
DS3 Out of Frame on Port 2
Framer Block Interrupt Active, Port 2
Port 2 Interrupt Active
Note
Unmask OOF interrupt on Port 2
Unmask Port 2 interrupts
GLOBAL
INTERRUPT
STATUS REGISTER
and INTERRUPT
ENABLE REGISTER
GL.ISR.PISRn
GL.ISRIE.
PISRIEn
INTERFACE INTERRUPTS
TRANSMIT SYSTEM
INTERRUPTS
PORT
INTERRUPTS
GLOBAL
INT

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