DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 246

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]) – These three bits indicate the rate at which errors are
inserted in the output data stream. One out of every 10
of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10
TEIR[2:0] value of 2 result in every 100
a TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process, the
new error rate will be started after the next error is inserted.
Bit 2: Bit Error Insertion Enable (BEI) – When 0, single bit error insertion is disabled. When 1, single bit error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) – This bit causes a bit error to be inserted in the transmit data stream if
manual error insertion is disabled (MEIMS = 0) and single bit error insertion is enabled. A 0 to 1 transition causes a
single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If
MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be
inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause a bit error to be inserted.
TEIR[2:0]
000
001
010
011
100
101
110
111
15
—
—
0
7
0
Error Rate
Disabled
1*10
1*10
1*10
1*10
1*10
1*10
1*10
14
—
—
0
6
0
-1
-2
-3
-4
-5
-6
-7
BERT.TEICR
BERT Transmit Error Insertion Control Register
(0,2,4,6)68h
th
TEIR2
bit being inverted. Error insertion starts when this register is written to with
13
—
0
5
0
TEIR1
12
—
0
0
4
n
246
bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value
TEIR0
11
—
0
3
0
BEI
10
—
0
2
0
th
TSEI
—
9
0
1
0
bit being inverted. A
MEIMS
—
8
0
0
0