DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 317

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 13: Remote Error Indication Maximum Error (REIME) – When 0, an REI error is generated by inserting a
value of 1h (single error) into the REI bits (G1[1:4]). When 1, an REI error is generated by inserting a value of 8h
(eight errors) into the REI bits.
Bit 12: Continuous Remote Error Indication Error Insertion Enable (CREIIE) – When 0, single remote error
indication (REI) error insertion is enabled. When 1, continuous REI error insertion is enabled, and REI errors will be
continuously transmitted if REIEI is high.
Bit 11: Remote Error Indication Error Insertion Enable (REIEI) – When 0, REI error insertion is disabled. When
1, REI error insertion is enabled.
Bit 10: Parity Block Error Enable (PBEE) – When 0, a parity error is generated by inverting a single bit in the B1
byte. When 1, a parity error is generated by inverting all eight bits in the B1 byte.
Bit 9: Continuous Parity Error Insertion Enable (CPEIE) – When 0, single parity (BIP-8) error insertion is
enabled. When 1, continuous parity error insertion is enabled, and parity errors will be transmitted continuously if
PEI is high.
Bit 8: Parity Error Insertion Enable (PEI) – When 0, parity (BIP-8) error insertion is disabled. When 1, parity (BIP-
8) error insertion is enabled.
Bit 5: Framing Byte Error Enable (FEE) – When 0, a framing bit error is generated by inverting a single bit in the
indicated byte. When 1, a framing byte error is generated by inverting all eight bits of the indicated byte.
Bits 4 to 3: Framing Error Control (FEIC[1:0]) – These two bits control the type of framing error event to be
inserted.
Bit 2: Framing Error Insertion Enable (FEI) – When 0, framing error insertion is disabled. When 1, framing error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) – This bit causes an error of the enabled type(s) to be inserted in the
transmit data stream if manual error insertion is disabled (MEIMS = 0). A 0 to 1 transition causes a single error to
be inserted. For a second error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and
this bit transitions more than once between error insertion opportunities, only one error will be inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause an error to be inserted.
00 = single A1 or A2 error (1 per sub-frame maximum).
01 = single POI (P#) error (1 per 2 sub-frames maximum).
10 = both an A1 and an A2 error in the same sub-frame.
11 = two POI (P#) errors in consecutive sub-frames.
15
—
—
0
7
0
14
—
—
0
6
0
PLCP.TEIR
PLCP Transmit Error Insertion Register
(1,3,5,7)52h
REIME
FEE
13
0
5
0
CREIIE
FEIC1
12
0
0
4
317
FEIC0
REIEI
11
0
3
0
PBEE
FEI
10
0
2
0
CPEIE
TSEI
9
0
1
0
MEIMS
PEI
8
0
0
0