DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 364

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 2: Receive FCS Errored Packet Count (REPC) – This read-only bit indicates that the receive FCS errored
packet count is non-zero.
Bit 1: Receive Aborted Packet Count (RAPC) – This read-only bit indicates that the receive aborted packet count
is non-zero.
Bit 0: Receive Size Violation Packet Count (RSPC) – This read-only bit indicates that the receive size violation
packet count is non-zero.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 7: Receive FCS Errored Packet Latched (REPL) – This bit is set when a packet with an errored FCS is
detected.
Bit 6: Receive Aborted Packet Latched (RAPL) – This bit is set when a packet with an abort indication is
detected.
Bit 5: Receive Invalid Packet Detected Latched (RIPDL) – This bit is set when a packet with a non-integer
number of bytes is detected.
Bit 4: Receive Small Packet Detected Latched (RSPDL) – This bit is set when a packet smaller than the
minimum packet size is detected.
Bit 3: Receive Large Packet Detected Latched (RLPDL) – This bit is set when a packet larger than the maximum
packet size is detected.
Bit 2: Receive FCS Errored Packet Count Latched (REPCL) – This bit is set when the REPC bit in the RPPSR
register transitions from zero to one.
Bit 1: Receive Aborted Packet Count Latched (RAPCL) – This bit is set when the RAPC bit in the RPPSR
register transitions from zero to one.
Bit 0: Receive Size Violation Packet Count Latched (RSPCL) – This bit is set when the RSPC bit in the RPPSR
register transitions from zero to one.
REPL
15
15
—
—
—
7
7
RAPL
14
14
—
—
—
6
6
PP.RSR
Packet Processor Receive Status Register
(1,3,5,7)CEh
PP.RSRL
Packet Processor Receive Status Register Latched
(1,3,5,7)D0h
RIPDL
13
13
—
—
—
5
5
RSPDL
12
—
12
—
—
4
4
364
Reserved
Reserved
RLPDL
11
11
—
3
3
Reserved
Reserved
REPCL
REPC
10
10
2
2
Reserved
Reserved
RAPCL
RAPC
9
1
9
1
Reserved
Reserved
RSPCL
RSPC
8
0
8
0