DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 172

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.10.6.2 Transmit M23 DS3 Frame Generation
M23 DS3 frame generation receives the incoming payload data stream, and overwrites the entire DS3 overhead bit
locations.
The multiframe alignment bits (M
respectively.
The sub-frame alignment bits (F
(1001) respectively.
The X-bits (X
programmable (automatic, 1, or 0). If the T3.TCR.ARDID is one then the T3.TCR.TRDI register bit controls this bit.
If the RDI is generated automatically (T3.TCR.ARDID=0), the X-bits are set to zero when one or more of the
indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are absent.
Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The P-bits (P
payload parity is calculated by performing modulo 2 addition of all of the payload bits after all frame processing has
been completed. P-bit generation is programmable (on or off). The P-bits will be generated if either P-bit generation
is enabled or frame generation is enabled.
If C-bit generation is enabled (T3.TCR.CBGD), the bit C
all of the other C-bits (C
(C
Overhead insertion may still overwrite the C-bit time slots even if C-bit generation is disabled.
Once all of the DS3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming DS3 signal is passed on directly to error insertion. Frame generation is
programmable (on or off). Note: P-bit generation may still be performed even if frame generation is disabled.
10.10.6.3 Transmit M23 DS3 Error Insertion
Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be
inserted are framing errors and P-bit parity errors.
The framing error insertion mode is programmable (F-bit, M-bit, SEF, or OOMF). An F-bit error is a single sub-
frame alignment bit (F
error is an error in all the sub-frame alignment bits in a sub-frame (F
single multiframe alignment bit (M
A P-bit parity error is generated by is inverting the value of the P-bits (P
error(s) can be inserted one error at a time, or continuously. The P-bit parity error insertion mode (single or
continuous) is programmable.
Each error type (framing or P-bit parity) has a separate enable. Continuous error insertion mode inserts errors at
every opportunity. Single error insertion mode inserts an error at the next opportunity when requested. The framing
multi-error insertion modes (SEF or OOMF) insert the indicated number of error(s) at the next opportunities when
requested; i.e., a single request will cause multiple errors to be inserts. The requests can be initiated by a register
bit (TSEI) or by the manual error insertion input (TMEI). The error insertion request source (register or input) is
programmable. The insertion of each particular error type is individually enabled. Once all error insertion has been
performed, the data stream is passed on to overhead insertion.
10.10.6.4 Transmit M23 DS3 Overhead Insertion
Overhead insertion can insert any (or all) of the DS3 overhead bits into the DS3 frame. The DS3 overhead bits X
X
TOHSOF). The P-bits (P
internally generated bit). The DS3 overhead insertion is fully controlled by the transmit overhead interface. If the
transmit overhead data enable signal (TOHEN) is driven high, then the bit on the transmit overhead signal (TOH) is
inserted into the output data stream. Insertion of bits using the TOH signal overwrites internal overhead insertion.
2
XY
, P
) will be treated as payload data, and passed through. C-bit generation is programmable (on or off). Note:
1
, P
2
, M
X
1
, F
1
and P
and X
XY
, and C
2
) are both overwritten with the calculated payload parity from the previous DS3 frame. The
XY
2
XY
) are both overwritten with the Remote Defect Indicator (RDI). The RDI source is
) error. An M-bit error is a single multiframe alignment bit (M
1
) are overwritten with zeros. If C-bit generation is disabled, then all of the C-bit timeslots
XY
and P
can be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, and
X1
1
2
, M
) are received as an error mask (modulo 2 addition of the input bit and the
, F
1
, M
2
X2
, or M
, F
2
, and M
X3
3
, and F
) error in each of two consecutive DS3 frames.
3
) are overwritten with the values zero, one, and zero (010)
X4
) are overwritten with the values one, zero, zero, and one
172
11
is overwritten with an alternating one zero pattern, and
X1
1
, F
and P
X2
, F
2
) in a single DS3 frame. P-bit parity
X3
, and F
1
, M
X4
2
). An OOMF error is a
, or M
3
) error. An SEF
1
,