DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 10

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3181/DS3182/DS3183/DS3184
Figure 10-49. FEAC Controller Block Diagram........................................................................................................ 188
Figure 10-50. FEAC Codeword Format................................................................................................................... 189
Figure 10-51. Line Encoder/Decoder Block Diagram .............................................................................................. 190
Figure 10-52. B3ZS Signatures ............................................................................................................................... 192
Figure 10-53. HDB3 Signatures............................................................................................................................... 192
Figure 10-54. BERT Block Diagram ........................................................................................................................ 193
Figure 10-55. PRBS Synchronization State Diagram.............................................................................................. 195
Figure 10-56. Repetitive Pattern Synchronization State Diagram........................................................................... 196
Figure 10-57. LIU Functional Diagram..................................................................................................................... 197
Figure 10-58. DS3/E3/STS-1 LIU Block Diagram.................................................................................................... 198
Figure 10-59. Receiver Jitter Tolerance .................................................................................................................. 201
Figure 13-1. JTAG Block Diagram........................................................................................................................... 372
Figure 13-2. JTAG TAP Controller State Machine .................................................................................................. 373
Figure 13-3. JTAG Functional Timing...................................................................................................................... 376
Figure 14-1. DS3184 Pin Assignments—400-Lead TE-PBGA................................................................................ 377
Figure 14-2. DS3183 Pin Assignments—400-Lead TE-PBGA................................................................................ 378
Figure 14-3. DS3182 Pin Assignments—400-Lead TE-PBGA................................................................................ 378
Figure 14-4. DS3181 Pin Assignments—400-Lead TE-PBGA................................................................................ 379
Figure 18-1. Clock Period and Duty Cycle Definitions............................................................................................. 384
Figure 18-2. Rise Time, Fall Time, and Jitter Definitions......................................................................................... 384
Figure 18-3. Hold, Setup, and Delay Definitions (Rising Clock Edge) .................................................................... 384
Figure 18-4. Hold, Setup, and Delay Definitions (Falling Clock Edge).................................................................... 385
Figure 18-5. To/From High-Z Delay Definitions (Rising Clock Edge)...................................................................... 385
Figure 18-6. To/From High-Z Delay Definitions (Falling Clock Edge) ..................................................................... 385
Figure 18-7. Micro Interface Nonmultiplexed Read/Write Cycle ............................................................................. 391
Figure 18-8. Micro Interface Multiplexed Read Cycle.............................................................................................. 392
Figure 18-9. E3 Waveform Template....................................................................................................................... 395
Figure 18-10. STS-1 Pulse Mask Template ............................................................................................................ 396
Figure 18-11. DS3 Pulse Mask Template................................................................................................................ 397
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