DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 197

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.16 Line Interface Unit (LIU)
10.16.1 General Description
The line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3, E3, or
STS-1 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. See
for the location within the DS318x device of the LIU.
Figure 10-57. LIU Functional Diagram
10.16.2 Features
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10.16.2.1 Transmitter
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10.16.2.2 Receiver
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Each Port Independently Configurable
Perform Receive Clock/Data Recovery and Transmit Waveshaping
Jitter Attenuators can be Placed in Either the Receive or Transmit Paths
Interface to 75Ω Coaxial Cable at Lengths Up to 380 meters (DS3), 440 meters (E3), or 360 meters (STS-1)
Use 1:2 Transformers on TX and RX
Require Minimal External Components
Local and Remote Loopbacks
Gapped clock capable up to 52MHz
Wide 50 ±20% transmit clock duty cycle
Clock inversion for glue-less interfacing
Unframed all-ones generator (E3 AIS)
Line build-out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor
AGC/equalizer block handles from 0 to 15dB of cable loss
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Clock inversion for glue-less interfacing
Per-channel power-down control
Clock Rate
Receive
Transmit
DS3/E3
DS3/E3
Adapter
LIU
LIU
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
IEEE P1149.1
JTAG Test
Access Port
FEAC
DS3 / E3
Framer
DS3 / E3
Transmit
Receive
Formatter
Buffer
Trace
Trail
HDLC
197
GEN
UA1
TX FRAC/
PLCP
RX FRAC/
PLCP
Rx Packet
Processor
Processor
Processor
Processor
RX BERT
Tx Packet
TX BERT
Rx Cell
Tx Cell
Microprocessor
Interface
FIFO
FIFO
Tx
Rx
Figure 10-57