DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 80

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-32. UTOPIA Level 3 Receive Multiple Cell Transfer Direct Mode
Figure 8-33
ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it has a complete
cell ready for transfer by asserting RPXA. On clock edge 5, the ATM device selects PHY port 'N'. On clock edge 6,
the ATM device indicates to PHY port 'N' that it is ready to accept a complete cell transfer by asserting REN. On
clock edge 8, PHY port 'N' starts a cell transfer by placing the first byte of cell data on RDATA, and asserting RSOX
to indicate the transfer of the first byte of the cell. On clock edge 9, PHY port 'N' deasserts RSOX as it continues to
place additional bytes of the cell on RDAT. On clock edge 11, the ATM device polls PHY device 'N'. On clock edge
12, PHY port 'M' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On
clock edge 12, PHY port 'N' indicates to the ATM device that it does not have a complete cell ready for transfer by
deasserting RPXA. On clock edge 15, the ATM device deselects PHY port 'N' and selects PHY port 'M' by
deasserting REN and placing PHY port 'M's address on RADR. On clock edge 16, the ATM device asserts REN.
On clock edge 17, PHY port 'N' stops transferring cell data. On clock edge 18, PHY port 'M' starts a cell transfer by
placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell.
On clock edge 19, PHY port 'M' deasserts RSOX as it continues to place additional bytes of the cell on RDATA.
Figure 8-33. UTOPIA Level 3 Receive Multiple Cell Transfer Polled Mode
RDXA[2]
RDXA[1]
RDXA[3]
RDXA[4]
RDATA
RSCLK
Cell From:
RADR
Transfer
RSOX
Cell From:
REN
Transfer
RADR
RSOX
RPXA
RDAT
RCLK
REN
shows a multiport receive-interface multiple cell transfer from different PHY ports. On clock edge 1, the
1
M
K
X
1
2
N
X
L
2
M
3
O
X
3
N
X
4
P
4
Q
O
X
5
5
N
X
P
6
H1
6
R
Q
X
7
H2
7
N
X
J
8
00h
H3
8
H1
K
R
9
…
80
9
H2
L
J
10
P42
10
…
…
…
11
PORT 1
P43
11
P43
N
L
12
P44
12
N
P44
M
O
13
P45
13
P45
N
P
14
P46
14
P46
Q
O
15
P47
15
P47
M
P
16
P48
16
P48
R
Q
17
17
M
X
J
01h
18
H1
18
H1
K
R
PORT 2
19
H2
19
M
H2
L
J
20
H3
20
P1
M
K