DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 75

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.5
8.3.5.1
Figure 8-25
the ATM device places address ‘00h’ on the address bus (which is mapped to Port 1). PHY device '1' (Port 1)
indicates to the ATM device that it can accept cell data by asserting TDXA[1]. On clock edge 4, the ATM device
selects PHY device '1'. On clock edge 5, the ATM device starts a cell transfer to PHY device '1' by asserting TEN,
placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the cell.
On clock edge 6, the ATM device deasserts TSOX as it continues to place additional bytes of the cell on TDATA..
On clock edge 13, PHY device ‘2’ asserts TDXA[2] to indicate to the ATM device that it is ready to accept cell data.
On clock edge 15, PHY device '1’ indicates that it cannot accept the transfer of a complete cell by deasserting
TDXA[1]. On clock edge 16, the ATM device deselects PHY device '1' and selects PHY device '2' by deasserting
TEN and placing PHY device '2's address on TADR. On clock edge 17, the ATM device starts the transfer of a cell
to PHY device '2' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the
transfer of the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues to place
additional bytes of the cell on TDATA.
Figure 8-25. UTOPIA Level 2 Transmit Cell Transfer Direct Mode
TDXA[2]
TDXA[1]
TDXA[3]
TDXA[4]
TDATA
TADR
TCLK
Transfer
Cell To:
TSOX
TEN
UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing
UTOPIA Level 2 Functional Timing
shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2,
1
2
3
4
5
H1
6
H2
7
H3
…
8
00h
9
P42
75
10
PORT 1
P43
11
P44
12
P45
13
P46
14
P47
15
P48
16
17
H1
01h
18
PORT 2
H2
19
H3
20
H4