DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 21

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3.19 FEAC Controller Features
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3.20 Trail Trace Buffer Features
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3.21 Bit Error Rate Tester (BERT) Features
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3.22 Loopback Features
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3.23 Microprocessor Interface Features
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3.24 Subrate Features (Fractional DS3/E3)
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Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode and optionally the G.751 Sn bit or the
G.832 NR or GC channels or PLCP F1, M1 or M2 bytes
RX data is forced to all ones during LOS, LOF and AIS detection to eliminate false packets
Each port has a dedicated FEAC controller for DS3/E3 link management
Designed to handle multiple FEAC code words without Host intervention
Receive FEAC automatically validates incoming code words and stores them in a 4-byte FIFO
Transmit FEAC can be configured to send one codeword, one codeword continuously, or two different code
words back-to-back to send DS3 Line Loopback commands
Terminates the FEAC channel in DS3 C-Bit Parity mode and optionally the Sn bit in E3 mode
Each port has a dedicated Trail Trace Buffer for E3-G.832 or DS3/E3 PLCP link management
Extraction and storage of the incoming G.832 or PLCP trail access point identifier in a 16-byte receive register
Insertion of the outgoing trail access point identifier from a 16-byte transmit register
Receive trace identifier unstable status indication
Each port has a dedicated BERT tester
Generation and detection of pseudo-random patterns and repetitive patterns from 1 to 32 bits in length
Pattern insertion/extraction in PLCP payload, DS3/E3 payload, DS3/E3 fractional payload or entire data stream
to and from the line interface
Large 24-bit error counter allows testing to proceed for long periods without host intervention
Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-
error rates)
Analog interface loopback – ALB (transmit to receive)
Line facility loopback – LLB (receive to transmit) with optional transmission of unframed all-one AIS payload
toward system/trunk interface
Framer diagnostic loopback – DLB (transmit to receive) with automatic transmission of DS3 AIS or unframed
all-one AIS signal toward line/tributary interface(s)
DS3/E3 framer payload loopback – PLB (receive to transmit) with optional transmission of unframed all-one
AIS payload toward system/trunk interface
System interface loopback – SLB (transmit to receive)
Simultaneous line facility loopback and framer diagnostic loopback
Multiplexed or non-multiplexed address bus modes
8 or 16-bit data bus modes
Byte swapping option in 16-bit data bus mode
Read/Write and Data Strobe modes
Ready handshake output signal
Global reset input pin
Global interrupt output pin
Two programmable I/O pins per port
Independent per-port built-in support for subrate DS3 or E3
Independent subrate operation for both RX and TX data paths
Subrate operation for each channel is totally independent from the other channels’ operation, i.e. all subrate
functions within the device are mutually exclusive
Three distinct subrate algorithms:
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