DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 48

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2 Detailed Pin Descriptions
Table 8-2. Detailed Pin Descriptions
n = 1,2,3,4 (port number). Ipu (input with pullup), Oz (output tri-stateable) (needs an external pullup or pulldown resistor to keep from floating),
Oa (Analog output), Ia (analog input), IO (bidirectional in/out). All unused input pins without pullup should be tied low.
TPOSn /
TLCLKn
TDATn
PIN
TYPE
O
O
Transmit Line Clock Output
TLCLKn: This signal is available when the transmit line interface pins are enabled
(PORT.CR2.TLEN). This clock is typically used as the clock reference for the TPOSn
/ TDATn and TNEG / TOHMOn signals, but can also be used as the reference for the
TOHMIn / TSOFIn, TFOHn / TSERn, TFOHENIn and TSOFOn / TDENn /
TFOHENOn signals.
This output signal can be inverted.
o
o
o
Transmit Positive AMI / Data Output
TPOSn: When the port line interface is configured for B3ZS, HDB3 or AMI mode and
the framer is not configured for one of the “-OHM” modes (see
transmit line interface pins are enabled (PORT.CR2.TLEN), a high on this pin
indicates that a positive pulse should be transmitted on the line. The signal is updated
on the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the TLCLKn line clock output pins, but it can be referenced to the
TCLKOn, TCLKIn, RLCLKn or RCLKOn pins. This output signal can be disabled
when the TX LIU is enabled.
This output signal can be inverted.
TDATn: When the port line interface is configured for UNI mode or the framer is
configured for one of the “-OHM” modes (see
interface pins are enabled (PORT.CR2.TLEN), the un-encoded transmit signal is
output on this pin. The signal is updated on the positive clock edge of the referenced
clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling
edge of the clock. The signal is typically referenced to the TLCLK line clock output
pins, but it can be referenced to the TCLKOn, TCLKIn, RLCLKn or RCLKOn pins
This output signal can be inverted.
o
o
o
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
CC52: 52 MHz +20 ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
CC52: 52 Mbps +20ppm
LINE IO
48
FUNCTION
Table
10-32) and the transmit line
Table
10-32) and the